A per-channel LSI codec for PCM communications

An LSI codec for voiceband signals is presented. A modified counting type encoding technique is employed to realize the codec, which uses coarse and fine reference current to discharge the integrating capacitor. The technique makes possible the realization of a high-speed counting-type codec for voice signals without imposing severe requirements on device parameters. This codec is composed of two LSI chips, i.e., a bipolar chip and an NMOS chip. An estimation sample of the LSI codec is fabricated and evaluated. Measured data of the codec performance are very close to the theoretically expected value. The performance assures that the device can be applied to channel banks, local switches, toll switches, and EPBXs.     

一种超高清激光电视系统的设计方案

文章介绍一种超高清激光电视系统的设计方案,详细阐述了方案的设计原理.系统TV SOC模块将电视信号处理成像素为4M×2N@f的超高清图像信号,图像处理模块对超高清图像信号进行采样、分割和倍频处理后得到2路（√2 M×√2）N@2f的高清图像信号,DMD驱动模块对2路高清图像信号进行合并处理得到（2√2M×√2N@2f）图像信号来驱动DMD芯片,DMD芯片投射出分辨率为（2√2M×√2N）的图像光;采用振镜使DMD投射的相邻帧图像光位置微移,从而显示出4M×2N@f的合成画面.该方案可以快速应用于超高清激光电视产品,具有广泛应用价值.     

A single-chip adaptive DPCM video codec

A differential pulse-code modulation (DPCM) video codec with two-dimensional intrafield prediction and adaptive quantizer is presented. An approach for the arithmetic implementation of the DPCM structure and the design of a test chip, fabricated in a 1.5 μm CMOS technology, is described. This is the first VLSI realization of a DPCM codec with adaptive quantizer. For the test chip transmitter or receiver mode, application as part of a three-dimensional interframe codec and processing of luminance or chrominance signals are optional. A line buffer and ten different quantizer characteristics are realized on-chip. Correct operation has been verified up to 26 MHz     

A single-board video codec using video image signal processors

This paper discusses a newly developed single-board video codec using Video Image Signal Processors (VISPs). The codec has both a CCITT H.261 mode and a proprietary mode. Two VISPs, one for encoding and one for decoding, are used. The board size is 210 by 295 mm, the maximum frame rate is about 7.5 f/s, and the picture size is 180 by 144 pels.     

一种高鲁棒性的高清视频在线识别

为了提高高清视频图像识别的正确率和鲁棒性,提出一种高鲁棒性的高清视频在线识别算法。首先采集视频图像序列,然后对视频图像进行置乱和压缩,提高其鲁棒性,最后对视频图像识别,并采用具体实验对本算方法进行仿真测试。实验结果表明,本文算法提高了视频识别的正确率,而且具有较好的实时性和鲁棒性,具有较高的实际应用价值。     

A high-speed digital filter LSI for video signal processing

A ninth-order symmetrical filter has been developed for use in two-dimensional (2-D) processing in TV video systems, especially in high-definition TV receivers. A 2-D filter that is composed of only two types of LSIs (one-dimensional (1-D) digital filter LSI and delay-line) is discussed. The architecture of the digital filter LSI and circuit techniques are presented to obtain high-speed operation, to save chip area, and to decrease power consumption. The order and the transfer function of the filter can be altered by means of the external terminals. The chip, achieved through 2-/spl mu/m CMOS technology, contains about 52000 transistors and occupies an area of 50 mm/SUP 2/. It operates at a high clock frequency of over 33 MHz, and dissipates only 600 mW of power.     

A variable bit rate video codec for asynchronous transfer modenetworks

The bandwidth flexibility offered by the asynchronous transfer mode (ATM) technique makes it possible to select picture quality and bandwidth over a wide range in a simple and straightforward manner. A prototype model of a video codec was developed that demonstrates the feasibility of both variable bit rate (VBR) coding and user-selectable picture quality. The VBR coding algorithm is discussed and it is shown how a stabilized quality is achieved and how this quality and associated bandwidth can be selected by the user. How error propagation is limited to reduce the visibility of cell losses is also discussed. Interfaces with the ATM network are analyzed, with emphasis on decoder synchronization and absorption of cell delay jitter. The VBR codec offers very good picture quality for videophony applications at an equivalent load of 5.9 Mb/s. Picture quality remains relatively constant, even for heavy motion     

一种应用于高清视频模拟前端的多功能开关电容可编程增益放大器

A multifunctional programmable gain amplifier(PGA) that provides gain and offset adjusting abilities for high-definition video analog front-ends(AFE) is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter(ADC) in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter(DAC) for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18- m process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of –220 to220 mV while consuming 10.1 mA from a 1.8 V power supply.     

A Q-band radio-over-fiber system for distribution of uncompressed high-definition video signals

A Q-band radio-over-fiber (RoF) system for transmission of uncompressed high-definition (HD) video signals is proposed and demonstrated. Three key photonic technologies are employed, i.e., the dispersion compensation based on a polarization modulator and a polarizer in the transmitter, the RF carrier extraction based on injection-locked optoelectronic oscillator and the frequency downconversion based on cascaded external modulations in the receiver. A proof-of-concept experiment is carried out. Results show that the proposed system supports 20-km wired and 0.5-m wireless distribution of uncompressed HD video signal. The cooperation of two antennas is also demonstrated, which provides a preliminary demonstration of intelligent RoF system.     

IPTV视频编解码标准比较与分析

介绍了我国具有自主知识产权的AVS编解码标准,以其中涉及到视频压缩编码的AVS第二部分(AVS1-P2)和第七部分(AVS1-P7)为基础,说明了AVS视频标准的结构和原理;深入介绍了变换和量化、帧内预测、帧间预测、熵编码等AVS视频标准的关键技术;并和其它两个MPEG-4、H.264国际标准,在编码效率、软硬件成本等性能方面进行了比较和分析,最后得出AVS在我国是有比较好的应用前景.     

VLSI architecture for a low-power video codec system

In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware–software (HW–SW) partitioning assuming power consumption, flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW–SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform.     

A PMC-driven methodology for energy estimation in RVC-CAL video codec specifications

In this paper, an energy estimation methodology based on performance monitor counters (PMC) is proposed to estimate the energy consumption of RVC-CAL video codec specifications. The proposed PMC-driven methodology is able to automatically identify the most appropriate events and training data to cover the main application characteristics. In addition, knowledge of the hardware platform employed is not required. Therefore, this methodology can be easily implemented on other PMC-available systems while keeping the estimation accuracy. It is worth noting that this is an attractive asset to analyze the energy consumption of RVC-CAL codec specifications. Besides, the methodology reduces the PMC redundancy and, thus, the overhead introduced when applied to on-line power management. Experimenting on two RVC-CAL decoders, H.264 and MPEG4 Part2 SP, a coarse estimation model based on instructions per cycle (IPC) and the proposed PMC-driven model are compared. The results show that the PMC-driven model can achieve for the H.264 and MPEG4 Part2 SP decoders average estimation errors of 5.95% and 5.01%, respectively, in comparison to the 17.11% and 13.65% average errors obtained with the IPC-based model. As a consequence, this methodology is suggested to be combined into the RVC framework to help the designer to have an overview of the energy consumption of the specification actors at earlier design stages.     

Highly scalable wavelet-based video codec for very low bit-rateenvironment

We introduce a highly scalable video compression system for very low bit-rate videoconferencing and telephony applications around 10-30 kbits/s. The video codec first performs a motion-compensated three-dimensional (3-D) wavelet (packet) decomposition of a group of video frames, and then encodes the important wavelet coefficients using a new data structure called tri-zerotrees (TRI-ZTR). Together, the proposed video coding framework forms an extension of the original zero tree idea of Shapiro (1992) for still image compression. In addition, we also incorporate a high degree of video scalability into the codec by combining the layered/progressive coding strategy with the concept of embedded resolution block coding. With scalable algorithms, only one original compressed video bit stream is generated. Different subsets of the bit stream can then be selected at the decoder to support a multitude of display specifications such as bit rate, quality level, spatial resolution, frame rate, decoding hardware complexity, and end-to-end coding delay. The proposed video codec also allows precise bit rate control at both the encoder and decoder, and this can be achieved independently of the other video scaling parameters. Such a scheme is very useful for both constant and variable bit rate transmission over mobile communication channels, as well as video distribution over heterogeneous multicast networks. Finally, our simulations demonstrated comparable objective and subjective performance when compared to the ITU-T H.263 video coding standard, while providing both multirate and multiresolution video scalability     

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-μm CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm×10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% of that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 μA, which is only 17% of that for the conventional CMOS design     

An adjustment-free single-chip video signal processing LSI for VHSVCR's

The authors have developed an adjustment-free single-chip video signal processing large scale integration (LSI) for VHS VCR's. This LSI's adjustment-free system was realized by using automatic feedback loop circuits. The complementary high-speed switch circuits play an important role in this system. It was possible to realize the complementary high-speed switch circuits, because this LSI has been fabricated with 2 μm bipolar process. This paper describes how the LSI has succeeded in being adjustment-free on frequency modulation (FM) carrier frequency/deviation and output video signal amplitude     

Rate estimate for regular LDPCA codec in distributed video coding

Accumulated low density parity check (LDPCA) codec is proposed for DISCOVER project in distributed video coding (DVC),which offers flexible coding rate.Although it can use feedback channel to adapt the...     

A single-board video signal processor module employing newlydeveloped LSI devices

A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel×128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system     

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t_RAS=50 ns (typical) at V_cc=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V_SS shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4-μm CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM     

A line terminating LSI using echo cancelling method for ISDNsubscriber loop transition

A 144-kb/s digital subscriber loop (DSL) transmission system based on hybrid transmission with an echo cancelling method is described. It incorporates advanced LSI technology to obtain compactness, low cost, and high reliability. An echo canceller (EC) LSI has been developed using CMOS technology. Combined with the multiplexing processor (MXP) LSI, the EC LSI provides basic DSL equipment functions. A specially arranged frame format with a newly developed digital phase-locked loop (DPLL) circuit for stable timing extraction, an automatic balancing network, and a two-stage echo canceller characterize the system. Using this line termination circuit, the DSL equipment showed a reach of over 6 km when used with 0.5 mm diameter cable for 160-kb/s bidirectional digital transmission     

An adapted H.261 two-layer video codec for ATM networks

An adaptive video codec which can maintain compatibility between the existing digital circuit switched networks and future ATM networks is described. It is based on two-layer coding principles, where in the base layer the H.261 standard video codec is employed. It is shown that a discrete cosine transform (DCT) in the second layer is unnecessary and can be replaced by a simple requantizer which finely quantizes the residue quantization distortions of the transform coefficients of the base layer. Characteristics of this quantizer in terms of nature of quantization and step sizes are studied. Efficient coding and addressing of residual distortions are described. Finally, a two-dimensional variable length code for the quantized residual distortions is given