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1.
In this paper, an improved active resonant snubber cell that overcomes most of the drawbacks of the normal zero-current transition (ZCT) pulsewidth-modulation (PWM) dc-dc converter is proposed. This snubber cell is especially suitable for an insulated gate bipolar transistor (IGBT) PWM converter at high power and frequency levels. The converter with the proposed snubber cell can operate successfully with soft switching under light-load conditions and at considerably high frequencies. The operation principles, a detailed steady-state analysis, and a snubber design procedure of a ZCT-PWM buck converter implemented with the proposed snubber cell are presented. Theoretical analysis is verified with a prototype of a 5-kW and 50-kHz IGBT-PWM buck converter. Additionally, at 90% output power, the overall efficiency of the proposed soft switching converter increases to about 98% from the value of 91% in the hard-switching case.  相似文献   

2.
A single-stage single-switch high- frequency electronic ballast topology is presented. The circuit topology is the integration of a buck power- factor-correction (PFC) converter and a class E resonant inverter with only one active power switch. The buck converter is operated in discontinuous conduction mode and at a fixed switching frequency, and constant duty cycle to achieve high power factor and it can be controlled easily. Detailed analysis of the operation and characteristics of the circuit is provided. Simulation results satisfy present standard requirements.  相似文献   

3.
A load-adaptive automatic switching frequency selection scheme is proposed to improve the power efficiency of a switching buck converter at light load condition. The buck converter operates in the continuous-conduction mode for heavy loading and the switching frequency is fixed at its maximum value. For light loading, the buck converter operates in the discontinuous-conduction mode and its switching frequency is automatically selected among a pre-defined set of frequencies according to the amount of the load current. The load current can be sensed indirectly by monitoring the on-time of power transistor because it is a function of the load current. With the proposed load-adaptive automatic switching frequency selection circuit, the power efficiency of a buck converter implemented in a 0.35-μm 2P4M BCDMOS technology is improved by 24.0-% when the load current load is 10-mA.  相似文献   

4.
This paper presents the analysis of a DC-AC power converter using a zero-voltage-switching (ZVS) commutation cell. First, the authors show the cell applied to the buck power converter. The stages of operation are presented along with the main current and voltage equations. Next, they adapt the power converter to the regenerative-operation mode. Hence, the full-bridge power converter at low-frequency operation is connected in the DC-DC output stage (at high frequency). The main switches commute at zero voltage. The power converter operated at constant frequency with pulse-width modulation (PWM), and neither overvoltage nor additional current stress was observed by digital simulation. A design example and experimental results obtained by prototype, rated at 275 V and 1 kW, are also presented  相似文献   

5.
By adding a suitable LC filter to the input of a buck power converter, it is possible to force the converter into discontinuous-input-voltage mode operation. A buck power converter in this mode of operation has useful properties such as power factor correction and soft turn-off switching. The operation, modeling, low-frequency behavior, and application of the power converter are studied. Experimental results verifying the theoretical predictions are also presented  相似文献   

6.
In this paper, a high switching frequency buck converter using insulated gate bipolar transistors (IGBTs) is presented. This was done by using an auxiliary branch made of an IGBT of the same type as the one used for the main switch and saturable inductors. The proposed topology allows both switches to be fully soft switched to keep the efficiency high over a wide load range. Because of its topology the open loop behavior of the converter can be unstable. A detailed small signal analysis is presented to explain this behavior and as a basis for the synthesis of a closed loop controller. Experimental measurements on a laboratory prototype demonstrated the accuracy of the small signal analysis and validated the operation of the auxiliary network. The resulting efficiency is around 92% over a 200 to 800W output power range and at a 80-kHz switching frequency  相似文献   

7.
An analytic basis is provided for a buck high-efficiency high-frequency zero-current-switching resonant DC/DC power converter. The current and voltage waveforms are derived for the steady-state operation. Design equations are then introduced for the switch duty cycle, maximum switching frequency, DC transfer function, peak currents and voltages, output power, and power conversion capability. Finally, the design procedure is presented along with the advantages and disadvantages of the converter, which are discussed in detail  相似文献   

8.
提出了一种采用单周期输出电压预测(SCOVP)技术的自适应导通时间(AOT)控制Buck变换器。该变换器可以在输入输出电压及负载变化时实现频率恒定,并可设置外部电阻使Buck变换器准确工作在高开关频率下。首先分析了传统AOT控制Buck变换器的开关频率产生漂移的原因,并提出了一种采用SCOVP技术的单脉冲计时器(OST)电路。其次通过单周期占空比预测输出电压信息,并根据预测的输出电压和负载电流补偿TON时间,实现了Buck的频率稳定。该变换器采用0.18μm BCD工艺进行电路设计。仿真结果表明,在2 MHz开关频率下,负载电流从1 A到5 A变化时,Buck变换器的最大频率变化ΔfSW仅13 kHz,负载平均频率变化ΔfSW/ΔILoad为3.24 kHz/A。同时,变换器频率设置准确度从88%提升到99.35%。  相似文献   

9.
An integrated digital controller for dc-dc switch-mode power supplies (SMPS) used in portable applications is introduced. The controller has very low power consumption, fast dynamic response, and can operate at programmable constant switching frequencies exceeding 10 MHz. To achieve these characteristics, three novel functional blocks, a digital pulse-width modulator based on second-order sigma-delta concept (Sigma-Delta DPWM), dual-clocking mode compensator, and nonlinear analog-to-digital converter are combined. In steady state, to minimize power consumption, the controller is clocked at a frequency lower than SMPS switching frequency. During transients the clock rate is increased to the switching frequency improving transient response. The controller integrated circuit (IC) is fabricated in a standard 0.18-mum process and tested with a 750-mW buck converter prototype. Experimental results show the controller current consumption of 55 muA/MHz and verify closed-loop operation at programmable switching frequencies up to 12.3 MHz. Simulation results indicating that this architecture can potentially support operation at switching frequencies beyond 100 MHz are also presented.  相似文献   

10.
This paper develops a power loss optimization method in a current fed zero-voltage switching (ZVS) two-inductor boost converter, which is suitable for the module integrated converter applications in grid interactive photovoltaic systems. The paper conducts the numerical analysis of the variable power loss components and establishes a set of the circuit parameters for an optimized operating point with a minimized average power loss. The ZVS two-inductor boost cell is fed from a sinusoidally modulated two-phase synchronous buck converter with an interphase transformer and produces a rectified sinusoidal voltage, which can be applied to an unfolding stage to generate the grid compatible voltage. The boost cell is also equipped with a resonant transition gate drive circuit to reduce the power loss in the drive circuit under high frequency operations. The experimental results for a prototype 1-MHz 100-W ZVS two-inductor boost converter are presented at the end of the paper.  相似文献   

11.
王巍  童涛  赵汝法  吴浩  郭家成  丁辉  夏旭  袁军 《微电子学》2023,53(4):647-653
在降压转换器中,为了在不同的负载情况下获得高效率,常采用的方法是在重载时使用脉冲宽度调制(PWM),在轻载时使用脉冲频率调制(PFM),因此需要模式切换信号去控制整个降压转换器的工作状态,同时模式切换信号也可以用于自适应改变功率级电路中的功率管栅宽,减小功率管的栅极电容,提高整体电路的效率。文章设计了一个自适应峰值电流模式切换电路,用于产生模式切换信号,其原理是监控峰值电流的变化,产生峰值电压,将峰值电压与参考电压进行比较,得到模式切换信号,以决定降压转换器是采用PFM模式还是PWM模式。仿真结果表明,在负载电流0.5~500 mA范围内,该电路可以在两种调制模式之间平稳切换,其峰值效率可提升到94%以上。  相似文献   

12.
An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.  相似文献   

13.
A new, continuous-time model for current-mode control [powerconvertors]   总被引:1,自引:0,他引:1  
A current-mode control power convertor model that is accurate at frequencies from DC to half the switching frequency is described for constant-frequency operation. Using a simple pole-zero transfer function, the model is able to predict subharmonic oscillation without the need for discrete-time z-transform models. The accuracy of sampled-data modeling is incorporated into the model by a second-order representation of the sampled-data transfer function which is valid up to half the switching frequency. Predictions of current loop gain; control-to-output; output impedance; and audio susceptibility transfer functions were confirmed with measurements on a buck converter. The audio susceptibility of the buck converter can be nulled with the appropriate value of external ramp. The modeling concentrates on constant-frequency pulse-width modulation (PWM) converters, but the methods can be applied to variable-frequency control and discontinuous conduction mode  相似文献   

14.
The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.  相似文献   

15.
High switching frequency associated with soft commutation techniques is a new trend in switching converters. Following this trend, the authors present a buck pulsewidth modulation converter, where the DC voltage conversion ratio has a quadratic dependence on duty cycle, providing a large step-down. By introducing two resonant networks, soft switching is attained, providing highly efficient operating conditions for a wide load range at high switching frequency. Contrary to most of the converters that apply soft-switching techniques, the switches presented are not subjected to high switch voltage or current stresses and, consequently, present low conduction losses. The authors present, for this converter, the principle of operation, theoretical analysis, relevant equations and simulation and experimental results  相似文献   

16.
超快速加载Buck变换器设计   总被引:1,自引:0,他引:1  
倪雨 《电子学报》2013,41(8):1598-1602
为了提高VRM的加载响应速度,该文分析了传统Buck变换器的最优加载过程,并基于传统Buck变换器提出了双输入Buck变换器电路方案,说明了其稳态工作过程和加载运行过程,以最优加载阈值为依据给出了附加电源的切换条件,并做了仿真对比研究.仿真和试验结果表明双输入Buck变换器较传统Buck变换器具有更快加载响应速度和更小输出电压跌落,且结构简单,易于设计和实现,适用于VRM主电路.  相似文献   

17.
This paper presents a study of the performance of high-voltage Si and 4H-SiC diodes in a DC-DC buck converter. Device operation in both hard- and zero-voltage switching conditions is presented with the help of measurements and two-dimensional (2-D) mixed device-circuit simulations. Experimental results show that SiC PiN diodes have a strong potential for use in high-speed high-voltage power electronics applications operating at high temperature. A combination of low excess carrier concentration and low carrier lifetime results in superior switching performance of the 4H-SiC diode over ultrafast Si diodes. Soft switching is shown to minimize the switching loss and allow operation at higher switching frequencies using Si diodes. The power loss of 4H-SiC diodes is dominated by conduction loss. Consequently, soft-switching techniques result in a marginal reduction in power loss. However, the low overall power loss implies that SiC diodes can be used at very high switching frequencies even in hard-switching configurations.  相似文献   

18.
提出了一种应用于48 V-1 V系统的隔离型混合模式降压变换器,利用飞电容和变压器实现高转换比应用下的高转换效率。混合变换器结合了开关电容变换器和开关电感变换器,其中飞电容承担了部分电压降,实现了功率开关管电压应力的降低。由于开关节点处的电压摆幅较小,开关损耗随之减小;通过使用更低压的功率开关管,实现功率开关管导通损耗减小。在此基础上,隔离型混合模式降压变换器通过时序控制可以实现软开关,进而实现功率开关管开关损耗减小,使得整体效率提升。在隔离型混合模式降压变换器中,飞电容还具有隔直电容的作用,可以防止变压器偏磁。在典型应用下,即在48 V输入电压、1 V输出电压、500 kHz开关频率下,峰值效率为94.84%。  相似文献   

19.
An on-chip buck converter which is implemented by stacking chips and suitable for on-chip distributed power supply systems is proposed. The operation of the converter with 3-D chip stacking is experimentally verified for the first time. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70 mA and a voltage conversion ratio of 0.7 with a switching frequency of 200 MHz and a 2 times2 mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35-mum CMOS and connected with metal bumps. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3% is also discussed.  相似文献   

20.
Experimental results are presented for buck and flyback zero-voltage-switched (ZVS) quasi-resonant converters (QRCs) operating above 5 MHz. A design procedure for a buck ZVS QRC is proposed that minimizes voltage stress to the power MOSFET transistor while maintaining zero voltage switching for specified ranges of input voltage and load resistance. A quasi-resonant gate drive scheme is also proposed and implemented in a buck converter. The drive is simple and provides high switching speed. Power dissipation in the gate drive is substantially reduced due to the quasi-resonant operation. The ZVS QRC technique described is suitable for very-high-frequency operation due to its ability to reduce dynamic turn-on losses, Miller effect, dv/dt, and di//dt and can be applied in distributed onboard power supplies  相似文献   

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