A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links

This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded by the improved two-stage limiting amplifiers and a 50-Ω output buffer, the receiver achieves high differential swings. For a bit-error rate (BER) of 10⁻¹² at 25 Gb/s, the measured transimpedance gain, bandwidth, sensitivity, and output swing are 63.17 dBΩ, 20.7 GHz, −10.3 dBm, and 352.7 mV, respectively. The power consumption of the entire receiver is 111.6 mW and the core area of the die is 640 μm × 135 μm.     

Si bipolar chip set for 10-Gb/s optical receiver

Three Si bipolar ICs, a preamplifier, a gain-controllable amplifier, and a decision circuit, have been developed for 10-Gb/s optical receivers. A dual-feedback configuration with a phase adjustment capacitor makes it possible to increase the preamplifier bandwidth up to 11.2 GHz, while still retaining flat frequency response. The gain-controllable amplifier, which utilizes a current-dividing amplifier stage, has an 11.4-GHz bandwidth with 20-dB gain variation. A master-slave D-type flip-flop is also operated as the decision circuit at 10 Gb/s. On-chip coplanar lines were applied to minimize the electrical reflection between the ICs     

High-gain transimpedance amplifier in InP-based HBT technology forthe receiver in 40-Gb/s optical-fiber TDM links

A monolithic integrated transimpedance amplifier for the receiver in a 40-Gb/s optical-fiber TDM system has been fabricated in an InP-based HBT technology. Despite its high gain (transimpedance of 2 kΩ in the limiting mode, 10 kΩ in the linear mode) the complete amplifier was realized on a single chip. Clear output eye diagrams were measured up to 43 Gb/s under realistic driving conditions. The voltage swing of 0.6 V_pp at the differential 50 Ω output does not change within the demanded input dynamic range of 6 dB. At the upper input current level even 48 Gb/s were achieved. The power consumption is approximately 600 mW at a single supply voltage of -5.5 V     

A BiCMOS limiting amplifier for SONET OC-3

This paper presents a Synchronous Optical NETwork (SONET) OC-3 155.52 Mb/s limiting amplifier, which is implemented in a 1.0 μm double-poly double-metal N-well BiCMOS technology. Composed of amplifier cells, a slicer, an output driver, and offset cancellation circuits, this limiting amplifier allows an input dynamic range of 36 dB (6 mV_pp~400 mV_pp) and provides a constant output 1 V _pp across a 50 Ω load for long-haul 40 km application. The active area of this limiting amplifier is 0.8 mm×3.0 mm. It consumes 130 mW from a single -5 V supply voltage     

1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.     

应用于千兆以太网的1-Gb/s 零极点对消CMOS跨阻放大器

A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.     

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.     

A wideband low-noise variable-gain BiCMOS transimpedance amplifier

A new monolithic variable gain transimpedance amplifier is described. The circuit is realized in BiCMOS technology and has measured gain of 98 kΩ, bandwidth of 128 MHz, input noise current spectral density of 1.17 pA/√(Hz) and input signal-current handling capability of 3 mA     

A transimpedance APD optical receiver operating at 10 Gb/s

The authors report an optical receiver which uses a separate-absorption-and-multiplication avalanche photodiode (SAM-APD) to achieve high sensitivity at a bit rate of 10 Gb/s. A transimpedance front end incorporating HEMT devices is used for high bandwidth and low noise. The sensitivity (bit-error rate of 10^-9) is -28.7 dBm for a return-to-zero signal, and -27.0 dBm for a nonreturn-to-zero signal     

BiCMOS variable gain transimpedance amplifier for automotive applications

A new BiCMOS variable gain transimpedance amplifier with a large area integrated photodiode for automotive applications is presented. Through careful control of the input pole position and the frequency response of the core amplifier, the bandwidth of the transimpedance amplifier varies from 112 to 300 MHz when its gain changes from 14.2 kOmega to 400 Omega. The proposed circuit configuration maintains a high voltage across a common anode photodiode, and its bandwidth in highest gain varies from 121 to 102 MHz over a temperature range of -40 to +140degC. Simulation results in a 0.6 mum Si BiCMOS technology are given. The amplifier consumes 16 mW from a 3.3 V supply.     

基于10Gb/s光互连的新型前均衡跨阻放大器

本文提出一种新型全均衡技术,以应用于改进调节式共源共栅跨阻放大器设计。此全均衡技术主要基于宽带串联电感π型网络技术和跨导倍增技术。这种（前均衡）技术的思想是在信号进入电路之前就对其进行补偿,并且不需要额外的功耗。此外,一种新型的密勒电容补偿技术用于后续的增益提高级,来更进一步的提高带宽。本设计的跨阻放大器基于台湾联合电子公司（UMC）的0.18 μm CMOS 工艺,并通过一个片上0.3pF的金属-半导体-金属（MIM）型电容来仿真实际的光电探测器电容。测试结果显示,此跨阻放大器带宽为8.2GHz,增益为57 dBΩ,由1.8V单端电压供电,总功耗仅为22mW.     

An auto-gain control transimpedance amplifier with low noise andwide input dynamic range for 10-Gb/s optical communication systems

This paper describes a 10-Gb/s transimpedance amplifier (TIA), fabricated in a 0.1-μm-p-HEMT technology. To improve the optical overload characteristics, an automatic gain control (AGC) circuit is included. The measured results show excellent performance, transimpedance of 63.3 dBΩ (1.46 kΩ), bandwidth of 8.0 GHz, and equivalent input noise current density of 6.5 pA/rtHz. When the bit error rate is 10^-9, the minimum sensitivity and the optical overload are -21.2 dBm, +4.3 dBm, respectively, using a 0.8 A/W pin photodiode (PD). The power dissipation is about 0.5 W from a single -5-V supply. The die area is 1.3×1.6 mm²     

A fully integrated SiGe receiver IC for 10-Gb/s data rate

A silicon germanium (SiGe) receiver IC is presented here which integrates most of the 10-Gb/s SONET receiver functions. The receiver combines an automatic gain control and clock and data recovery circuit (CDR) with a binary-type phase-locked loop, 1:8 demultiplexer, and a 2 ⁷-1 pseudorandom bit sequence generator for self-testing. This work demonstrates a higher level of integration compared to other silicon designs as well as a CDR with SONET-compliant jitter characteristics. The receiver has a die size of 4.5×4.5 mm2 and consumes 4.5 W from -5 V     

A RGC-based,low-power,CMOS transimpedance amplifier for 10Gb/s optical receivers

ABSTRACT

In this paper, a new low-power transimpedance amplifier (TIA) based on a modified Regulated Cascode (RGC) circuit structure followed by a closed-loop post-amplifier is proposed for 10 Gb/s applications. The main objective of this work is to reduce the power consumption while, the frequency bandwidth of the proposed amplifier is increased considerably. The booster of a conventional RGC is modified by a cascoded transistor and its effect on the performance of the circuit is studied mathematically, which are verified by simulations. The bandwidth extension is occurred due to increasing the gain of the booster amplifier in the RGC stage, which isolates further the input capacitance and results in a reduced input resistance value hence, a higher input pole frequency is obtained in comparison with other conventional RGC structures. On the other hand, by using an active inductive peaking technique, the frequency of the output pole is also increased which results in a further extension of the frequency bandwidth for the proposed circuit. The proposed TIA is simulated using 90 nm CMOS technology parameters, which shows a 50.5 dBΩ transimpedance gain, 7.3 GHz frequency bandwidth and 1.22 µA_rms input referred noise value for only 1 mW of power consumption at 1.2 V supply voltage.     

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial datacommunications

A 2.125-Gb/s transmitter meeting the specifications of the emerging ANSI Fiber Channel standard has been developed using BiCMOS technology. This transmitter features (1) a fully bipolar 10:1 multiplexer (MUX) and a 2.125-GHz retimer for high-accuracy transmission of data, (2) an emitter-coupled logic (ECL) CMOS analog phase-locked loop, (3) pure ECL-level output for direct connection to the currently available optical modules, and (4) BiCMOS process technology that includes 0.25-μm CMOS devices and 20-GHz bipolar devices. The LSI serializes 32-bit-wide, 53.125-Mb/s data into 2.125-Gb/s data through a CMOS 8B10B encoder. The chip area is 3×2 mm², and the power dissipation is 860 mW     

A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON

In this paper, we present an integrated 155-Mb/s burst-mode receiver (BMR) for passive optical network (PON) applications. The chip has been designed to receive optical signals over a wide dynamic range (-30 to -8 dBm) and temperature range (-40°C to +85°C). The chip was implemented using a 0.8-μm 35-GHz SiGe BiCMOS technology and occupies an area of 4.3×4.9 mm² with a power consumption of 500 mW from a supply voltage of 5 V (3.3 V for the digital PECL output). In the receiver analog front end, we used a low-noise wide-band transimpedance amplifier followed by a nonlinear gain stage to cover a wide signal range without changing the transimpedance gain. The circuit dynamically adjusts the receiver threshold voltage through a feedback loop, thus optimizing the pulsewidth distortion and canceling the optical as well as the electrical offset voltages     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

Wide dynamic range parallel feedback transimpedance amplifier for 10 Gb/s optical links

This paper presents the design and implementation of a new wide dynamic range parallel feedback (PF) transimpedance amplifier (TIA) for 10 Gb/s optical links. The wide dynamic range is attributed to the novel TIA architecture employing both shunt-shunt and shunt-series feedback networks. The outstanding features of the TIA are wide dynamic range, high gain, low power consumption and design simplicity. A prototype implemented in a 0.5 μm SiGe BiCMOS technology and operating at −3.3 V power supply features an 18.4 dBm dynamic range with a BER less than 10⁻¹², an optical sensitivity of −16 dBm, optical overload of +2.4 dBm, a bandwidth of 8.27 GHz, a gain of 950 Ω and a power consumption of 189 mW. The new parallel feedback architecture offers improved overload and noise performance when compared to previously reported, state of the art, single feedback TIA designs and meets all the 10 Gigabit Ethernet and short-reach OC-192 SONET specifications. Ricardo Andres Aroca received the B.S. (Hons) degree in electrical engineering from the University of Windsor, Canada, and the M.S. degree from the University of Toronto, Canada, in 2001 and 2004, respectively. In 2000 he spent two 4 month internships with Nortel Networks in the Microelectronics Department. Mr. Aroca received the Natural Sciences and Engineering Research Counsel of Canada (NSERC) Postgraduate Scholarship award in 2002. He is currently working toward the Ph.D. degree at the University of Toronto where his research interests lie in the area of high-frequency integrated circuits for wireless and wireline communication systems. C. Andre T. Salama received the B.A.Sc. (Hons.) M.A.Sc. and Ph. D. degrees, all in Electrical Engineering, from the University of British Columbia in 1961, 1962 and 1966 respectively. From 1962 to 1963 he served as a Research Assistant at the University of California, Berkeley. From 1966 to 1967 he was employed at Bell Northern Research, Ottawa, as a Member of Scientific Staff working in the area of integrated circuit design. Since 1967 he has been on the staff of the Department of Electrical and Computer Engineering, University of Toronto where he held the J.M. Ham Chair in Microelectronics from 1987 to 1997. In 1992, he was appointed to his present position of University Professor for scholarly achievements and preeminence in the field of microelectronics. In 1989-90, he was awarded the ITAC/NSERC Research Fellowship in information technology. In 1994, he was awarded the Canada Council I.W. Killam Memorial Prize in Engineering for outstanding career contributions to the field of microelectronics. In 2000, he received the IEEE Millenium Medal. In 2003, he received the Outstanding Lifetime Achievement Award from the Canadian Semiconductor Technology Conference for seminal and outstanding contributions to semiconductor device research and promotion of Canadian University research in microelectronics. In 2004, he received the NSERC Lifetime Achievement Award of Research Excellence for outstanding and sustained contributions to the field of microelectronics and the Networks of Centres of Excellence (NCE) Recognition Award for research excellence and outstanding leadership.He was associate editor of the IEEE Transactions on Circuits and Systems in 1986–88 and a member of the International Electron Devices Meeting (IEDM) Technical Program Committeein 1980–82, 1987–89 and 1996–98. He was the chair of the Solid State Devices Subcommittee for IEDM in 1998 and was a member of the editorial board of Solid State Electronics from 1984 to 2002. He is presently a member of the editorial board of the Analog IC and Signal Processing Journal and the Technical Program Committee of the International Symposium on Power Semiconductor Devices and ICs (ISPSD) and the Technical ProgramCommittee of the International Symposium on Low Power Electronics and Design (ISLPED). He chaired the technical program committee of ISPSD in 1996 and was the general chair for the conference in 1999.Dr. Salama is the Scientific Director of Micronet, a network of centres of excellence focussing on microelectronics research and funded by the Canadian Government and Industry. He has published extensively in technical journals, is the holder of eleven patents and has served as a consultant to the semiconductor industry in Canada and the U.S. His research interests include the design and fabrication of semiconductor devices and integrated circuits with emphasis on deep submicron devices as well as circuits and systems for high speed, low power signal processing applications. Dr. Salama is a Fellow of the Institute of Electrical and Electronics Engineers, a Fellow of the Royal Society of Canada, a Fellow of the Canadian Academy of Engineering, a member of the Association of Professional Engineers of Ontario, the Electrochemical Society and the Innovation Management Association of Canada.