Low-power clock distribution using multiple voltages and reduced swings

Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low-power clock tree by distributing the clock signal at a lower voltage and translating it to a higher voltage at the utilization points. Two low-power schemes are used: reduced swing and multiple-supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the NTRS. Our experimental results show that power savings of an average of 45% are possible for a 0.25 /spl mu/m technology using multiple supply voltages, and about 32% using a single external supply voltage.     

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.     

基于异或门自选通的低功耗时钟树综合方案

本文介绍一种降低时钟网络功耗的方法。该方法基于电路中寄存器本身的状态值,在采用异或门进行自选通后构建时钟树结构,从而减少时钟信号额外翻转,降低芯片功耗。将该方法应用于一款基于SMIC0.18μmEflash 2p4m工艺下的非接触式智能卡芯片的物理设计。仿真结果表明,与传统时钟树综合方法相比,芯片功耗降低了10.7%。     

Efficient shield insertion for inductive noise reduction in nanometer technologies

With high clock frequencies, faster transistor rise/fall time, wider wires, and the use of Cu material interconnects, interconnect inductive noise is becoming an important design metric in digital circuits. An efficient technique to reduce the inductive noise of on-chip interconnects is to insert shields among signal wires. An efficient solution for the min-area shield insertion problem to satisfy given explicit noise bounds in multiple coupled nets is provided. The proposed algorithm determines the locations and number of shields needed to satisfy certain noise constraints. Experimental results show that the proposed approach minimizes the number of shields required to satisfy the noise constraints and uses less runtime than the best alternative reported approach.     

Power characteristics of inductive interconnect

The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeoff, therefore, exists between short-circuit and dynamic power in inductive interconnects. The short-circuit power increases with wider linewidths only if the line is underdriven. The power characteristics of inductive interconnects therefore may have a great influence on wire sizing optimization techniques. An analytic solution of the transition time of a signal propagating along an inductive interconnect with an error of less than 15% is presented. The solution is useful in wire sizing synthesis techniques to decrease the overall power dissipation. The optimum linewidth that minimizes the total transient power dissipation is determined. An analytic solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 80% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.     

Clock Mesh Network Design with Through‐Silicon Vias in 3D Integrated Circuits

Many methodologies for clock mesh networks have been introduced for two‐dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three‐dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through‐silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.     

Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect

In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of wire inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of the transistors are optimized to accelerate the signal propagation while consuming minimum power. In 90-nm CMOS technology, STR design achieved a delay improvement of 14% over the conventional repeater design. Furthermore, 20% power reduction is achieved for iso-delay, and 8% delay improvement for iso-power compared with the repeater design. The proposed technique has also been applied to a clock distribution network, reducing clock power by 26%.     

Reduced clock swing domino logic

A reduced clock swing domino logic gate for 50% reduction in power consumption in clock networks is presented. The original full swing gate works properly at reduced swing with a better noise tolerance and small loss of performance while simple resizing allows the same speed, power and noise figures     

A low-power reduced swing global clocking methodology

In this brief, we investigate the potential of reduced swing clock networks for low-power applications. We designed and laid out a full swing conventional and a reduced swing H-tree clock distribution network in 0.13-/spl mu/m CMOS technology operating at 500 MHz. In the reduced swing clock network, the swing was reduced in the global clock distribution network and was restored to the full swing in the local clock distribution domains. The post-layout simulation results of this research shows that a power saving of 22% under nominal operating condition is feasible.     

Automated low-power technique exploiting multiple supply voltagesapplied to a media processor

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance     

Clock Buffer Polarity Assignment for Power Noise Reduction

Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 50% and 51%, respectively.      

Optimization of Driver Preemphasis for On-Chip Interconnects

In modern digital systems, on-chip interconnects have become the system bottleneck, limiting the performance of high-speed clock distributions and data communications in terms of speed and power dissipation. An inverse signaling analysis is developed to optimize the driving signal waveforms for lossy interconnects. By specifying the performance parameters, i.e., the signal swing and edge rate of the interconnect output signal, the corresponding input signals can be derived analytically. The result can be used to guide and optimize the design of interconnect preemphasis drivers. Numerical examples are shown for both lossy RC and RLC distributed lines. Analysis shows that optimized driving voltage and current can increase the interconnect bandwidth without voltage overshoot at the output. The significance of an interconnect inductance is also evaluated with this technique.     

A low-swing clock double-edge triggered flip-flop

A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V_t transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network     

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

Transistor threshold voltage (V_t) scaling causes higher power consumption by increasing the subthreshold leakage and short-circuit currents in CMOS circuits. Leakage currents are significant contributors to the overall power consumption of digital systems-on-chip as threshold voltage, channel length, and gate oxide thickness are reduced with CMOS technology scaling. A new dual-pullup/dual-pulldown (DPU/DPD) repeater is proposed in this paper for higher energy efficiency in low-voltage and low-frequency applications. The standby mode leakage power consumption is reduced by 59.11% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 1.0V in a 45 nm CMOS technology. The short-circuit currents are suppressed by selectively employing high-V_t transistors in the repeaters. The clock network with the proposed buffer lowers the active mode energy consumption by up to 24.91% as compared to a conventional clock tree under equal silicon area constraint. Post layout results reveal that the statistical spread of clock skew in the DPU/DPD H-tree is also 20.60% lower than the conventional H-tree network.     

10‐Bit 200‐MS/s Current‐Steering DAC Using Data‐Dependant Current‐Cell Clock‐Gating

This letter proposes a low‐power current‐steering digital‐to‐analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current‐source cells in which the data will not be changed. The 10‐bit DAC is implemented using a 0.13‐μm CMOS process with V_DD=1.2 V. Its area is 0.21 mm². It consumes 4.46 mW at a 1‐MHz signal frequency and 200‐MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25‐MHz and 10‐MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1‐MHz and 50‐MHz signal frequencies, respectively.     

Coupled electro-thermal modeling and optimization of clock networks

In this paper a coupled electro-thermal model is used for the optimal design of the clock distribution tree of a high performance microprocessor. Such approach allows simultaneously to take into account both thermal and electrical constraints. In particular timing issues such as clock delay from the root of the tree to the leaves and skew between the leaves are optimized by a suitable wire and buffer sizing. At the same time the lifetime constraints of clock wires that are affected by the electromigration, enhanced by the high temperature reached in interconnects due to the Joule self-heating, are checked and respected.     

Generalised Elmore delay expression for distributed RC tree networks

A generalised Elmore delay (GED) expression is proposed which can be applied directly to distributed RC tree networks. Using this expression, the signal delay caused by interconnects such as those in LSIs can be estimated more simply and accurately than using the conventional Elmore delay model.<>     

基于Encounter的低功耗时钟树综合研究

以基于Cadence CCOPT引擎设计时钟树为例,介绍了以降低时钟树功耗为主要目的,使用门控技术,以及选择合适缓冲器、反相器构建时钟树的方法。通过完成物理设计动态仿真和功耗分析的数据表明,在保证时序收敛的前提下,使用门控技术和选用不同缓冲器、反向器对整个时钟树的功耗及性能影响进行分析。实验结构表明,对使用门控技术芯片的功耗在不同的操作条件下,整个时钟树上的功耗节省约50%;适合使用缓冲器和方向器构建时钟树。同时,在使用达到相同驱动的能力缓冲器和反相器情况下,使用缓冲器的时钟树较使用反相器的时钟树节省30%。     

Dynamically De-Skewable Clock Distribution Methodology

In a typical clock distribution scheme, a central clock signal is distributed to several sites on the integrated circuit (IC). Local regenerators at these sites buffer the clock signal for the logic in regions close to the regenerator. Minimizing the skew between the clocks at these regeneration sites is critical. In recent times, this is becoming harder due to increasing intra-die processing variations. In this paper, we describe a novel technique to distribute a clock signal from a central location to several sites on a VLSI IC. Our technique uses a buffered H-tree and includes circuitry to dynamically remove any skew that may result due to intra-die processing variations. While existing approaches to deskewing a clock tree have utilized several phase detection circuits (number of phase detectors dependent on the number of clock regenerators), our method requires only one phase detector. Also, in our approach, the resolution of the phase detector is inconsequential unlike existing techniques. Our deskewing technique can be applied dynamically, either at boot time or periodically during the operation of the IC. Using a six-level H-tree clock distribution network with process variations deliberately included, we demonstrate that our technique can reduce skews as high as 300 ps down to just 3 ps. We compare our clock tree with traditional buffered and unbuffered H-tree networks.      

Scaling theory in modern VLSI

Discusses the scaling rules for VLSI that pertain to the total wire length and the clock speed. The analysis indicates that the total wire length is not increasing as rapidly as standard scaling theory would indicate. This results from over-scaling of the cell size reduction from one generation to the next (as predicted by Moore [1975]). However, the total wire length is still increasing at a rate that will cause significant power dissipation in the interconnects and indicates the need for new locally interconnected architectures. Moreover, the over-scaling of cell size reduction also raises the possible limitations that arise as the cell size is reduced faster than the gate length. We also discussed the effects of scaling on on-die clock speed. While gate-array clock speeds are scaling slower than the scaling rules would predict (a problem for large multi-chip architectures), clock speeds in modern VLSI chips track the scaling rule quite accurately