Development of an electrothermal simulation tool for integrated circuits: Application to a two-transistor circuit

In this paper a methodology for performing electrothermal analyses on integrated circuits is introduced. Using the relaxation method, standard electrical and thermal simulators, which are often used in the design process, are coupled through an efficient interface program. The simulator is capable of performing steady-state and transient analysis at device and chip levels. A variable-time-step technique has been implemented to reduce the computational time for a given set of computational resources. The simulator has been validated on different structures such as the bipolar junction transistor to predict the temperature distribution and the device performance in an amplifier circuit and an integrated current-mirror circuit. The simulation results are compared to experimental results to verify the performance of the electrothermal simulator and the accuracy of the thermal model. Simulation results demonstrate that the approach is suitable to model the thermal effects of integrated circuits in a more time-efficient, accurate and user-friendly fashion.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

Electrothermal Monte Carlo Simulations of InGaAs/AlGaAs HEMTs

Results from the application of our electrothermal simulator to n-type 0.15 μm gate In_0.15Ga_0.85As-Al_0.28Ga_0.72As HEMT structures are presented. The simulator involves an iterative procedure which alternately solves the Heat Diffusion Equation (HDE) and executes a Monte Carlo electronic transport algorithm. The net thermal flux generated during each Monte Carlo stage, calculated from the net rate of phonon emission, is fed into the thermal solution; the resulting temperature map is then used in the following Monte Carlo iteration. The HDE is solved through application of a novel analytical thermal resistance matrix technique which allows calculation of temperatures solely within the region of interest while including the large-scale boundary conditions. A novel charge injection scheme is applied for the treatment of side ohmic contacts, which avoids anomalous generation of thermal flux in adjacent regions. The characteristic ‘thermal droop’ is found in the I-V characteristics of the simulated device. Associated temperature distributions are shown to be spatially non-uniform with peak values and spatial locations dependent upon bias and the length of the containing die. Electron drift velocities and energies along the HEMT channel exhibit the largest shift on the inclusion of thermal self-consistency below the drain end of the gate, not at the location of the temperature peak.     

Aspects of the Electrocaloric Behavior of Ferroelectric Thin Films: A Review of the Predictions of the Landau-Ginzburg Theory

A thermodynamic model is used to investigate the electrocaloric response of thin film perovskite ferroelectrics under the influence of differing electrical, thermal and mechanical boundary conditions including bias and driving field, temperature, lateral clamping and misfit strain. A comparison of the electrothermal properties of ferroelectric solid solutions comprised of BaTiO₃, PbTiO₃ and/or SrTiO₃ illustrates the influence of composition on electrocaloric properties. Computations made for (001) textured polycrystalline BaTiO₃ films on IC-friendly substrates quantify the effects of thermal stresses. The combined results provide insights concerning how the deposition temperature, substrate material and composition can be adjusted to obtain desired electrocaloric response.     

Structure and properties of PP/TiO2 based polymer nanocomposites

ABSTRACT

The transient pulse testing is used in bridgewire-charges to measure the electrothermal performance non-destructively rather than by the conventional inspection. The conventional inspection has the disadvantage of destruction with a number of products tested, while the transient pulse testing can give a dynamic electrothermal curve at a user's command. In addition, the transient pulse testing can be used to measure a passel of products one by one rather than by a statistical spot check. Unfortunately, a statistic spot check cannot provide the firing reliability of products efficiently. The other way round, the transient pulse testing may put an end to the possibility of loss for users absolutely. The reason that the transient pulse testing is not devastating for products is that these mixtures of a product have a required thermal stability, and then are simultaneously able to be responded reliably by a very small pulse current. We have determined that these red matches based on Si/Pb₃O₄/DDNP mixtures electrothermal responsibility curves. Firing performance, measurements of the transient pulse testing, and electrothermal parameters are presented in this paper.     

A novel approach to extracting extrinsic resistances for equivalent circuit model of nanoscale MOSFET

A novel extrinsic resistance extraction method of MOSFET at V_gs = V_ds = 0 V from S‐parameter measurements is presented in this paper. Simulated and measured results of 90‐nm gatelength MOSFET device with a 8 × 0.6 × 12 µm gatewidth (number of gate finger × unit gate width × cells) are compared, and good agreement has been obtained up to 50 GHz. Furthermore, comparisons between the proposed approach and other three methods published are also made in this paper. Copyright © 2016 John Wiley & Sons, Ltd.     

Electrothermal stability of uniform arrays of one‐port elements

Power electronic elements are often built employing arrays of devices designed to evenly share high currents over a large number of single devices. In some situations, mismatch in current sharing can occur causing temperature differences between elements of the array. These differences can trigger electrothermal instability phenomena and even device destruction. In this paper, we consider the electrothermal dynamic behavior of arrays composed of identical one‐port elements. We first introduce a simplified model of the thermal paths and of the elements composing the array that allows the analysis of the behavior of the electrothermal system. Then, we investigate from a mathematical standpoint dynamic effects governing current sharing and possible situations causing hot spots with consequent device destruction. These results are compared with simulations of detailed non‐linear models confirming predictions given by the simplified model. Copyright © 2008 John Wiley & Sons, Ltd.     

A Quantum Mechanical Approach for the Simulation of Si/SiO2 Interface Roughness Scattering in Silicon Nanowire Transistors

In this work, we present a quantum mechanical approach for the simulation of Si/SiO₂ interface roughness scattering in silicon nanowire transistors (SNWTs). The simulation domain is discretized with a three-dimensional (3D) finite element mesh, and the microscopic structure of the Si/SiO₂ interface roughness is directly implemented. The 3D Schrödinger equation with open boundary conditions is solved by the non-equilibrium Green’s function method together with the coupled mode space approach. The 3D electrostatics in the device is rigorously treated by solving a 3D Poisson equation with the finite element method. Although we mainly focus on computational techniques in this paper, the physics of SRS in SNWTs and its impact on the device characteristics are also briefly discussed.     

Full Band Monte Carlo Simulation of Wurtzite AlGaN/GaN MODFETs

We present full band Monte Carlo simulations of a wurtzite Al_0.15Ga_0.85N/GaN modulation-doped field-effect transistor (MODFET). We found that without inclusion of the piezoelectric effect, the electron concentrations in the channel are much lower than obtained from experimental data. The calculated I _ds-V _ds curves show a strong negative differential resistance, which is a feature observed in experimental devices. Self-heating effects are usually believed to be the main cause of the negative differential resistance. Our simulations do not include self-heating, and this would indicate that at least part of what is observed is also caused by the drift-velocity behavior vs. electric field of the narrow conduction channel. For a 0.2 m gate MODFET, the simulations yield a maximum trans-conductance G _m 250 mS/mm with V _G = 1.0 V and V _ds = 5.0 V. When V _G = 0.0 V and V _ds = 8.0 V, we obtain a maximum cutoff frequency f _T = 180 GHz with I _d = 1159 mA/mm.     

适用于器件级到系统级热仿真的IGBT传热模型

提出一种基于器件到系统的等级与传热网络结构本身的多时间尺度特征建立绝缘栅双极型晶闸管(IGBT)传热模型的建模方法。基于热传导理论和经典Cauer传热RC网络结构,建立IGBT传热网络结构模型,查明单层与多层热网络结构的结温运行规律以及简化标准与方法。在此基础上,以器件到系统对IGBT传热模型的不同需求为主线,以器件封装结构各层时间常数的不同时间尺度为切入点,建立适用于器件级到系统级热仿真的IGBT传热模型。仿真与实验结果验证了模型的正确性与高效性。所建立的IGBT传热模型对于查明IGBT器件的传热网络结构特征与结温运行规律,实现电力电子器件到系统的独立与联合仿真具有一定的理论意义和应用价值。     

Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

In this paper, we propose a laterally graded-channel pseudo-junctionless (GPJL) MOSFET for analog/RF applications. We examine the dynamical performance of GPJL MOSFET and compare it with the common junctionless (JL) MOSFET architecture using a 2-D full-band electron Monte Carlo simulator (MC) with quantum correction. Our results indicate that the GPJL MOSFET outperforms the conventional JL MOSFET, yielding higher values of drain current (I _ds), transconductance (g _m), and cutoff frequency (f _t). Further, the emerging electric field and velocity distributions, as a consequence of the channel engineering introduced by the GPJL MOSFET, result in lower output conductance (g _ds) and higher early voltage (V _ea). The preeminence of the GPJL transistor over the JL transistor is further illustrated by showing improvements on the intrinsic voltage gain (A _vo) in the subthreshold regime, to as high as 61 %. These results indicate that our proposed GPJL MOSFET yields improvement in the analog/RF performance metrics as compared to JL MOSFETs.     

Concentration‐dependent minority carrier lifetime in an In0.53Ga0.47As interdigitated lateral PIN photodiode model based on spin‐on chemical fabrication methodology

The fitted parameters for the analytic function used to specify the doping dependence of minority carrier lifetimes for In_0.53Ga_0.47As (InGaAs) is described in this paper. This model together with other carrier models was used to develop an interdigitated lateral PIN photodiode utilizing InGaAs as the absorbing layer. We propose the usage of spin‐on chemicals such as spin‐on dopants and spin‐on glass to form the p+ wells, n+ wells and the surface passivation layer of the device hence providing a cheap and easy solution versus the conventional epitaxial growth methodology. The modeled device achieved dark currents of 0.21 nA and capacitance of 2.87 nF at an operating voltage of 5 V. Optical illumination at a wavelength of 1550 nm and power of 10 W/cm² enabled the device to achieve responsivity of 0.56 A/W and external quantum efficiency of 44%. The −3 dB frequency response of the device was at 8.93 GHz and signal‐to‐noise ratio is 36 dB. The developed device shows close correlation with experimentally developed devices developed using other fabrication methodologies. The results of this work would be useful in the thorough development of InGaAs‐based devices based on spin‐on chemical fabrication methodology using commercial device simulation packages. Copyright © 2010 John Wiley & Sons, Ltd.     

Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I_D-V_G and I_D-V_D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.     

The compact d.c. electrothermal model of power MOSFETs for SPICE

This paper concerns the problem of modelling of power MOS transistors in SPICE. In the paper the new form of the electrothermal d.c. model (ETM) of the considered class of power devices is proposed. The ETM is based on the modified Shichman–Hodges model, in which the generation current, the breakdown voltage, the sub‐threshold region, the thermally dependent series resistances and self‐heating are included. The device inner temperature calculated from the thermal model is the sum of the ambient temperature and the product of the electrical power dissipated inside the device and its thermal resistance. The presented model has been verified experimentally. The results of calculations and measurements of MTD15N06V (ON Semiconductor) and IRF840 (International Rectifier) transistors are given as well. Copyright © 2009 John Wiley & Sons, Ltd.     

双馈抽水蓄能机组用中点箝位式三电平变流器损耗与结温分布

针对双馈抽水蓄能机组(DFPSU)运行工况转换频繁,分析不同运行工况下中点箝位式(NPC)三电平变流器功率器件损耗及结温分布。基于DFPSU运行特点,以机侧变流器单相桥臂功率模块为例,研究了不同运行工况下各个功率器件开关动作和电流通路,理论上分析了器件损耗分布不均现象;基于功率器件导通损耗和开关损耗计算模型,建立其热网络等效电路和结温计算模型,考虑DFPSU控制策略,并基于PLECS平台建立了NPC三电平变流器功率器件电热耦合仿真模型;对机组在发电、电动和调相运行工况下的器件损耗和结温分布进行仿真。理论分析与仿真结果表明,不同运行工况下器件损耗不同,变流器中间位置的主开关和箝位二极管的损耗和平均结温最大,且机组在同步转速点附近器件结温波动最大。     

计及灰水负荷预测的区域型热补偿系统调控策略

传统供暖手段以热电联产机组作为主要热源，由于热电联产机组具有电热耦合的特性，因此运行时会产生热电负荷不匹配问题。为缓解这一问题，提出了一种集中供暖与区域型热补偿系统共同参与的供暖手段。对用户侧的灰水生产情况进行灰水生产活动预测，量化预计可回收热能，并结合光热电站的余热，将二者一同作为集中供暖的补偿热源。根据用户侧的热负荷特性以及光热电站和灰水热能回流系统的供热特性，构建区域型热补偿系统的运行优化模型，使用模型预测控制方法制定系统模型的调控策略。最后，通过设置算例仿真对比可知，所提出的调控策略能够回收利用原本废弃的热能，在实现供暖目标的同时保证了系统的经济性和环保性。     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

Thermal model of MOSFET with SELBOX structure

In this article, we present the thermal characteristics of the MOSFET with SELBOX structure. It is observed that the device shows a reduction in the self-heating effect and exhibits improved static and dynamic thermal behavior. A thermal model is developed to explain the thermal behavior of SELBOX structure. The model was evaluated using simulation implemented by Silvaco TCAD tools. Results show the effectiveness of the structure for the minimization of the self-heating effect (SHE) observed in SOI devices. Further, the results obtained from the simulation studies fit into the model showing the validity of the thermal circuit model.