A low-cost digital frequency testing approach for mixed-signal devices using ΣΔ modulation

This paper presents a digital approach to frequency testing of Analogue and mixed-signal (AMS) circuits. This approach is aimed at facilitating low-cost test techniques for system-on-chip (SoC) devices, rendering the test of mixed-signal cores compatible with the use of a low-cost digital tester. Analogue test signal generation is performed on-chip by low pass filtering a sigma–delta (ΣΔ) encoded bit-stream. Analogue harmonic test response analysis is also performed on-chip using square wave modulation and ΣΔ modulation. Since both analogue signal generation and test response analysis are digitally programmable on-chip, compatibility with a low-cost digital tester is ensured. Optimisation of test signatures is discussed in detail as a trade-off between fault and yield coverage. A 0.18 μm CMOS implementation of this BIST technique is presented, including some experimental results.     

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.     

Utilizing On-chip Resources for Testing Embedded Mixed-signal Cores

For mixed-signal cores on System-on-a-Chip (SoC) platforms, the current methodology in test development is to use special test modes for block isolation such that mixed-signal cores are accessible from the chip boundary through a well-defined interface. Since the access mechanism to the core is preserved, this method facilitates fast test development when the core is re-used on another SoC. In order to obtain the shortest per-device test times on low-cost test platforms, we explore the option of operating the SoC in its designed functional mode where all on-chip resources are fully available for test support. We demonstrate this new method for a microcontroller with embedded ADCs. For high-volume products, the ultimate target is to minimize test costs by maximizing the efficiency of testing multiple devices in parallel on one tester. We demonstrate two benefits of testing in a functional mode that increases parallel test efficiency: (1) Simultaneous testing of multiple on-chip cores, and (2) On-chip post-processing to reduce the amount of test data.     

Test throughput for mixed-signal devices

People encounter mixed-signal system-on-a-chip (SOC) devices in our daily lives in a broad range of products. Consumer products like PDAs, automobiles, and appliances all contain microcontrollers, battery management, and power chips; these can be mixed-signal devices. They use broadband products such as set-top boxes, cable modems, DSL, and DVD players that contain mixed-signal devices. Wireless products, cordless phones, cellular phones, WLAN, Bluetooth, GPS receivers, and cable tuners also contain mixed-signal SOC devices. The content of the mixed-signal SOC device is characterized by different types of cores. They may be analog cores or digital cores. Many applications include mixed analog and digital cores such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). These devices can provide complete system functionality on a single chip. One of the important principles to improving test economics is to ensure that test times are as low as possible. When testing, it is important that the test system is not adding overhead time. Beyond fast test software, the device-limited test speed is approached when tester operations execute in parallel with device operation. The architecture of the test system is key when approaching test times that are device limited. This can be achieved with a test system architecture that controls instrumentation precisely in device clock time. Mixed-signal device testing has adopted the use of DSP techniques to obtain a set of test measurements from large data sets. Each core within the device can produce data simultaneously. In the case of the device described earlier, there may be three video converters and five audio converters, all producing large amounts of data.     

Cost and performance analysis for mixed-signal system implementation: system-on-chip or system-on-package?

Advances in integrated circuits and packaging technologies provided us more implementation options for mixed-signal systems. Emerging technologies are represented by system-on-chip (SoC) and system-on-package (SoP). In order to make a design decision for optimal system implementation, it is hence becoming more and more important to address the cost and performance issues for various implementation options early in a system deign phase. In this paper, we develop a modeling technique for a priori cost and performance estimations for mixed-signal system implementations. The performance model evaluates various noise isolation technologies, such as using guard rings, increasing the separation between digital and analog/RF circuitry parts, using special substrate materials (e.g., silicon-on-insulator), and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or "virtual components," yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, are considered. Finally, an efficient computation algorithm, namely COMSI, was developed for cost estimation under various mixed-signal performance constraints. Case studies for SoC and SoP integration are performed using COMSI.     

Development of the Area-Reducing Active “Coil-Enhancement” Principle, Practiced Onto an ADSL–POTS Splitter

This paper describes the theory behind the “coil-enhancement” principle: The impedance of an inductor is made controllable as a function of the frequency by means of a transconductance function ${g}_{m} ({s})$ that is located in the feedback loop. In order to show the potential of the coil-enhancement circuit, the effect of several basic transconductance functions onto the synthesized impedance is presented. The specific case of ${g}_{m} ({s}) sim {s}^{-1}$ produces the coil-enhancement situation and is discussed in detail. One drawback of the coil-enhancement circuit is found in the series resistance of a second inductor, also positioned in the feedback loop. The influence of this series resistance onto the synthesized impedance is addressed and a work-around is presented. A newly developed active “plain old telephone service” (POTS) splitter, based upon the coil-enhancement principle, is derived from a fully passive POTS splitter in which two large inductors are merged together into one active inductor. The active POTS splitter is fully tested and is found compliant with the standard “TS 101 952-1-1 V1.2.1 (option A)” of the European Telecommunications Standards Institute. The area reduction that comes together with the passive-to-active conversion is 40%.      

一种基于8 bit CPU核的混合SoC验证平台的设计

提出了一种基于8 bit CPU的混合信号SoC的验证平台.该平台能够完成IP模块验证、软硬件协同验证、混合验证等关键验证流程.该验证平台已经成功地应用在某混合信号SoC的设计上,并在0.35 μm CMOS工艺上进行了实现.该验证平台对其它混合SoC设计具有一定的参考作用.     

The test search for true mixed-signal cores

The well-known method towards testing mixed-signal cores is functional testing and essentially measuring key parameters of the core. However, especially if performance requirements increase, and embedded cores are considered, functional testing becomes technically and economically less attractive. A more cost-effective approach could be accomplished by a combination of reduced functional tests and added structural tests. In addition, it will also improve the debugging options for cores. Basic problem remains the large computational effort for analogue structural testing. In this paper, we introduce the concept of Testability Transfer Function for both analogue as well as digital parts in a mixed-signal core. This opens new possibilities for efficient structural testing of embedded mixed-signal cores, thereby adding to the quality of tests and/or enhanced diagnostic capabilities.     

“Split ADC” Calibration for All-Digital Correction of Time-Interleaved ADC Errors

The “split analog-to-digital converter (ADC)” architecture enables fully digital calibration and correction of offset, gain, and aperture-delay mismatch errors in time-interleaved ADCs. The calibration of $M$ interleaved ADCs requires $2M + 1$ half-sized ADCs, a minimal increase in analog complexity. Each conversion is performed by a pair of half-sized ADCs, generating two independent outputs that are digitally corrected using estimates of offset, gain, and aperture-delay errors. The ADC outputs are averaged to produce the ADC output code. The difference of the outputs is used in a calibration algorithm that estimates the error in the correction parameters. Any nonzero difference drives a least-mean-square feedback loop toward zero difference, which can only occur when the average error in each correction parameter is zero. A simulation of a 4 : 1-time-interleaved 16-bit 12-MSps successive-approximation-register ADC shows calibration convergence within 400 000 samples.      

Test infrastructure design for mixed-signal SOCs with wrapped analog cores

Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications.     

An Erbium Fiber Fabricated by the “Core-Suction” Technique

An erbium doped fiber preform having a lead germanate erbium glass core with silica cladding was fabricated by a newly developed technique named “Core-Suction”. This preform was then drawn into fiber and fiber cross-section, loss spectrum and refractive index profile measured. A 30 cm piece of the manufactured fiber was spliced to a standard silica fiber using a commercial available splicer. This spliced fiber was then used to setup an erbium doped fiber amplifier (EDFA) and gain spectrum of the amplifier measured. Distributed gain of the manufactured erbium fiber was measured using an optical frequency domain reflectometry (OFDR) based optical backscatter reflectometer (OBR). It is demonstrated that the “Core-Suction” technique can be used to make a high-gain amplifier that is compatible with conventional silica fibers.      

Digital Background-Calibration Algorithm for “Split ADC” Architecture

The “split ADC” architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.      

基于V93000的SoC中端口非测试复用的ADC和DAC IP核性能测试方案

 SoC(System-on-a-Chip)芯片设计中,由于芯片测试引脚数目的限制以及基于芯片性能的考虑,通常有一些端口不能进行测试复用的IP(Intellectual Property)核将不可避免地被集成在SoC芯片当中.对于端口非测试复用IP核,由于其端口不能被直接连接到ATE(Automatic Test Equipment)设备的测试通道上,由此,对端口非测试复用IP核的测试将是对SoC芯片进行测试的一个重要挑战.在本文当中,我们分别提出了一种基于V93000测试仪对端口非测试复用ADC(Analog-to-Digital Converter)以及DAC(Digital-to-Analog Converter)IP核的性能参数测试方法.对于端口非测试复用ADC和DAC IP核,首先分别为他们开发测试程序并利用V93000通过SoC芯片的EMIF(External Memory Interface)总线对其进行配置.在对ADC和DAC IP 核进行配置以后,就可以通过V93000捕获ADC IP 核采样得到的数字代码以及通过V93000 采样DAC IP 核转换得到的模拟电压值,并由此计算ADC以及DAC IP 核的性能参数.实验结果表明,本文分别提出的针对端口非测试复用ADC以及DAC IP 核测试方案非常有效.     

Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device

In this paper, a wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device such as resonator is presented. Wet etching technique combined with dry etching technique is utilized to achieve a “Y-shaped” through wafer interconnection structure to shorten the TSV in order to reduce cost. Ansoft ${hbox {HFSS}}^{rm TM}$ 3-D electromagnetic simulator is used to assess the transition properties of signal with frequency of the new interconnection structure. Sn solder bonding is utilized to achieve simultaneous TSV connection and cavity hermetic sealing. Average shear strength of 19.5 Mpa and excellent leak rate of around ${hbox {1.9}} times {hbox {10}} ^{-9}~{hbox {atm cc/s}}$ have been achieved, which meet the requirements of MIL-STD-883E. Kevin structure is also fabricated to measure the resistance of the metallized TSV, the resistance of the “Y-shaped” through wafer interconnection and the contact resistance of the Cu/Sn IMC bond joint.      

Data Handling Limits of On-Chip Interconnects

With shrinking feature size and growing integration density in the deep sub-micrometer (DSM) technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This paper presents a two-fold approach for evaluating the signal and data carrying capacity of on-chip interconnects. In the first approach, the wire is modeled as a linear time invariant (LTI) system and a frequency response is studied. The second approach addresses delay and reliability in interconnects from an information theoretic perspective. Simulation results for an 8-bit-wide bus in 0.1-$mu$m technology are presented for both approaches. The results closely match to a similar optimal bus clock frequency that will result in the maximum data transfer rate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. The first approach achieves this higher transmission rate using ideal signal shapes, instead of square pulses, while the second approach uses coding techniques to eliminate high delay cases to generate a higher transmission rate. It is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these “good” signals arriving early can be used to predict/correct the “few” signals that arrive late.      

A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources

The test of analog & RF circuits at wafer-level suffers from both quality and throughput limitations, especially due to probing issues and limited count of expensive instrumentation resources. Since final test after packaging guarantees product performances, constraints on wafer-level test can be relaxed. This paper investigates a signal acquisition protocol based on the use of digital tester channels to perform the demodulation of analog/RF signals. Due to the large availability of such hardware resources on most testers, this approach allows to setup a multi-site strategy, thus increasing the test throughput. The fundamental concept is to capture the signal through the 1-bit comparator available in a digital tester channel and to process the resulting bit stream to retrieve the analog/RF signal characteristics. In this paper, the proposed solution is illustrated for the demodulation of Frequency-Modulated (FM) and Amplitude-Modulated (AM) signals. Both simulation and experimental results obtained with a Verigy 93K platform are presented.     

An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.      

Moving average filter for spur reduction in subsampling fractional PLLs

A mono-bit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is co-designed with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS three-dimensional (3D) heterogeneous integration using the wafer-level bonding technique. The measurable signal frequency within?+?15 to???25 dBm power is up to 7.5 GHz with a 14-GHz clock. Compared to an integrated circuit (IC) with a traditional InP or CMOS technologies, the proposed chip could benefit from both InP and CMOS technology. In the heterogeneous integration, InP devices provide high operating frequency, broad signal bandwidth, and large input signal dynamic range, while CMOS devices achieve complex function with low power consumption. In this way, the system FoM is improved for a mono-bit digital receiver while the system power consumption is kept the same. This work also shows the great potential of the 3D heterogeneous integration for the high-performance mixed-signal and multifunction radio-frequency ICs.

     

Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog

Nowadays, the semiconductor industry directs its attention to mixed-signal System-on-Chip (SoC) applications. Main targets are the creation of accurate and fast mixed-signal SoC designs, composed of both digital and analog components, and the reduction of time to market for this kind of integrated circuits (ICs). In order to bring a mixed-signal SoC faster to the market, higher system-level simulation speed is required, with respect to traditional modeling approaches. Real Number Modelling (RNM) could be an effective solution. In this work, a sigma-delta analog-to-digital converter (ADC), a voltage-controlled oscillator (VCO) and a digital phase-locked loop (PLL) are implemented as real number models using SystemVerilog. This paper is an extended version of work previously published by the authors. Herein, more accurate and parameterizable models were created, while their validation process is analyzed and achieved using a novel metric for accuracy estimation. The proposed models’ parameterizability enhances the usability of the models to various SoC designs. Aim of this work is to underline the RNM effectiveness provided by SystemVerilog, and exhibit a way to apply RNM for modeling and simulation of widely used analog/mixed-signal (AMS) blocks. The presented real number models were compared to Verilog-A, Verilog-AMS, and transistor-level SPICE models. All tests showed that the proposed real number models based on SystemVerilog demonstrate noteworthy improvement on simulation efficiency, with respect to previous works in the literature, preserving simultaneously sufficient accuracy.