Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces

The mobility-thickness dependence in SOI films is clarified. Measurements in fully depleted SOI MOSFETs show that the low-field mobility at the front channel decreases by thinning the Si film or by sweeping the back gate from depletion into accumulation. We demonstrate that this mobility degradation is only apparent, being related to the potential value at the surface facing the channel. This opposite-surface potential induces an intrinsic vertical field which adds to the usual gate-related field. The mobility drop simply indicates a deviation from the low-field condition which cannot be achieved. We propose an updated model for proper extraction and interpretation of the low-field mobility. Pseudo-MOSFET results reveal the existence of a similar additional vertical field in bare SOI wafers, induced by charges present on the unpassivated surface. This intrinsic field increases in thinner films and affects pseudo-MOSFET conduction. The mobility decrease measured in SOI wafers with thinner films reflects the increasing impact of the intrinsic field and does not imply any degradation in quality of film-BOX interface.     

Modeling of Surface-Roughness Scattering in Ultrathin-Body SOI MOSFETs

A rigorous surface-roughness scattering model for ultrathin-body silicon-on-insulator (SOI) MOSFETs is derived, which reduces to Ando's model in the limit of bulk MOSFETs. The matrix element of the scattering potential reflects the fluctuations of both the wavefunction and the potential energy. The matrix element reflecting the fluctuation of the wavefunction is expressed in an integral form which can be considered as a generalized Prange-Nee term-to which it is equivalent in the limit of an infinitely high insulator-semiconductor barrier-giving more accurate results in the case of a finite barrier height. The matrix element reflecting the fluctuation of the potential energy is due to the Coulomb interactions originating from the roughness-induced fluctuation of the electron charge density, the interface polarization charge, and the image-charge density. The roughness-limited low-field electron mobility in thin-body SOI MOSFETs is obtained using the matrix elements that we have derived. We study its dependence on the silicon body thickness, effective field, and dielectric constant of the insulator.     

Two-dimensional simulation and measurement of high-performanceMOSFETs made on a very thin SOI film

Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-Å-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation     

Low-field mobility and carrier transport mechanism transition in nanoscale MOSFETs

This paper extends the flux scattering method to study the carrier transport property in nanoscale MOSFETs with special emphasis on the low-field mobility and the transport mechanism transition. A unified analytical expression for the low-field mobility is proposed, which covers the entire regime from drift-diffusion transport to quasi-ballistic transport in 1-D, 2-D and 3-D MOSFETs. Two key parameters, namely the long-channel low-field mobility (μ0) and the low-field mean free path (λ0), are obtained from the experimental data, and the transport mechanism transition in MOSFETs is further discussed both experimentally and theoretically. Our work shows that λ0 is available to characterize the inherent transition of the carrier transport mechanism rather than the low-field mobility. The mobility reduces in the MOSFET with the shrinking of the channel length; however, λ0 is nearly a constant, and λ0 can be used as the "entry criterion" to determine whether the device begins to operate under quasi-ballistic transport to some extent.     

In Situ Comparison of Si/High- $kappa$ and $hbox{Si}/ hbox{SiO}_{2}$ Channel Properties in SOI MOSFETs

Detailed measurements of front- and back-channel characteristics in advanced SOI MOSFETs (ultrathin Si film, high-kappa, metal gate, and selective epitaxy of source/drain) are used to reveal and compare the transport properties at the corresponding Si/high- kappa (HfO₂ or HfSiON) and Si/SiO₂ interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage, and subthreshold swing. As compared with Si/SiO₂, the low-field mobility is lower at the Si/high-kappa interface and increases less rapidly at low temperature, reflecting additional scattering mechanisms governed by high-kappa and neutral defects.     

A temperature-dependent SOI MOSFET model for high-temperatureapplication (27 °C-300 °C)

A temperature-dependent model for long-channel silicon-on-insulator (SOI) MOSFETs for use in the temperature range 27 °C-300 °C, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the temperature-dependent effects in SOI MOSFETs (such as threshold-voltage reduction, increase of leakage current, decrease of generation due to impact ionization, and channel mobility degradation with increase of temperature) which are influenced by the uniqueness of SOI device structure, i.e. the back gate and the floating film body. The model is verified by the good agreement of the simulations with the experimental data. The model is implemented in SPICE2 to be used for circuit and device CAD. Simple SOI CMOS circuits are successfully simulated at different temperatures     

On the modeling of surface roughness limited mobility in SOI MOSFETs and its correlation to the transistor effective field

In this paper, we discuss in detail the modeling of surface roughness (SR) scattering in single- and double-gate silicon-on-insulator (SOI) MOSFETs, where the conventional formulation based on the expected value of the electric field cannot be used. By reconsidering the Ando's original approach, we show that a model based on the eigenfunction derivatives at the Si-oxide interface can be naturally extended to SOI MOSFETs, and, furthermore, we also derive a formulation based on appropriate integrals of the eigenfunctions in the silicon film, which must replace the expected value of the field used in bulk MOSFETs. All the analytical identities used in the derivation of the model have been verified by using numerically calculated eigenvalues and wavefunctions. Our results indicate that, in ultrathin-film SOI MOSFETs, the effective field is no longer a good metric for the SR scattering and, furthermore, SR scattering affects the total mobility even at lower inversion densities than it does in bulk transistors.     

Physics-Based Modeling of Hole Inversion-Layer Mobility in Strained-SiGe-on-Insulator

The hole inversion-layer mobility of strained-SiGe homo- and heterostructure-on-insulator in ultrathin-body MOSFETs is modeled by a microscopic approach. The subband structure of the quasi-2-D hole gas is calculated by solving the 6times6koarrldrpoarr Schrodinger equation self-consistently with the electrostatic potential. The model includes four important scattering mechanisms: optical phonon scattering, acoustic phonon scattering, alloy scattering, and surface-roughness scattering. The model parameters are calibrated by matching the measured low-field mobility of two particularly selected long-channel pMOSFET cases. The calibrated model reproduces available channel-mobility measurements for many different strained-SiGe-on-insulator structures. For the silicon-on-insulator MOS structures with unstrained-Si channels, the silicon-thickness dependence resulting from our model for the low-field channel mobility agrees with previous publications.     

Observation of mobility enhancement in ultrathin SOI MOSFETs

The mobility in n-channel SOI MOSFETs exhibits a significant increase as the SOI film becomes thinner than 1000 Å. At a 500 Å SOI thickness, the mobility values are distributed in the 700-1100 cm²/Vs range, which are obviously higher than the value in a bulk MOSFET having an identical doping concentration. The observed mobility enhancement has been explained by a decrease in the vertical electric field, associated with the complete depletion of the SOI film     

Influences of buried-oxide interface on inversion-layer mobility inultra-thin SOI MOSFETs

This paper reports on a study of the inversion-layer mobility in n-channel Si MOSFETs fabricated on a silicon-on-insulator (SOI) substrate. In order to make clear the influences of the buried-oxide interface on the inversion-layer mobility in ultra-thin film SOI transistors, SOI wafers of different quality at the buried-oxide interface were prepared, and the mobility behaviors were compared quantitatively. The transistors with a relatively thick SOI film exhibited the universal relationship between the effective mobility and the effective normal field, regardless of the buried-oxide interface quality. It was found, however, that Coulomb scattering due to charged centers at the backside interface between SOI films and buried oxides has great influence on the effective mobility in the thin SOI thickness region, depending on the buried-oxide interface quality. This means that Coulomb scattering due to charged centers at the buried-oxide interface can degrade the mobility with decreasing SOI thickness, unless the SOI wafer quality at the buried-oxide interface is controlled carefully     

Off-leakage and drive current characteristics of sub-100-nm SOI MOSFETs and impact of quantum tunnel current

This paper estimates the off-leakage current (I/sub off/) and drive current (I/sub on/) of various SOI MOSFETs by simulations based on the hydrodynamic-transport model; the band-to-band tunneling (BBT) effect at the drain is taken into consideration. Here, the simulations are done for SOI structures with a thick channel where the distinct quantization of energy is irrelevant to the present results. It is shown that merging hydrodynamic transport with the BBT effect is indispensable if realistic I/sub off/ estimates are to be achieved. It is shown that the symmetric double-gate SOI MOSFET does not always offer better drivability than other SOI MOSFETs, and that a single-gate SOI MOSFET with carefully selected parameters exhibits superior performance to double-gate SOI MOSFETs. It is also demonstrated that the quantum tunnel current is not significant, even in 20-nm channel SOI MOSFETs. The results suggest that we can still employ the conventional semi-classical method to estimate the off-leakage current of sub-100-nm channel low-power SOI MOSFETs.     

Novel SOI p-channel MOSFETs with higher strain in si channel usingdouble SiGe heterostructures

We have studied p-channel advanced SOI MOSFETs using double SiGe heterostructures fabricated by the combination of SIMOX and high-quality strained-Si/SiGe regrowth technologies, in order to introduce higher strain in Si channel. It was revealed that this double SiGe structure of second Si_0.82Ge_0.18Si_0.93Ge_0.07 allows the second SiGe layer to relax by about 70%, because of the elastic energy balance between the second and the first-SiGe layers. As a result, the strain of Si layer on this double SiGe structure becomes higher than that of the single SiGe structure. Strained SOI p-MOSFETs using the double layer SiGe structure exhibited higher hole mobility than that of strained-SOI MOSFETs with single Si_0.9Ge_0.1 structure. The hole mobility enhancement of 30% and 45% was achieved in the strained-SOI MOSFETs with double SiGe structures, compared to that of the universal curve and the control-SOI MOSFETs, respectively     

Advanced SOI p-MOSFETs with strained-Si channel onSiGe-on-insulator substrate fabricated by SIMOX technology

We have newly developed an advanced SOI p-MOSFET with strained-Si channel on insulator (strained-SOI) structure fabricated by SIMOX (separation-by-implanted-oxygen) technology. The characteristics of this strained-SOI substrate and electrical properties of strained-SOI MOSFETs have been experimentally studied. Using strained-Si/relaxed-SiGe epitaxy technology and usual SIMOX process, we have successfully formed the layered structure of fully-strained-Si (20 nm)/fully-relaxed-SiGe film (290 nm) on uniform buried oxide layer (85 nm) inside SiGe layer. Good drain current characteristics have been obtained in strained-SOI MOSFETs. It is found that the hole mobility is enhanced in strained-SOI p-MOSFETs, compared to the universal hole mobility in an inversion layer and the mobility of control SOI p-MOSFETs. The enhancement of the drive current has been kept constant down to 0.3 μm of the effective channel length     

[110] strained-SOI n-MOSFETs with higher electron mobility

We have recently developed [110]-surface strained silicon-on-insulator (SOI) n-MOSFETs. The strained-silicon (Si) layer with the strain of about 0.6% has been fabricated on a relaxed SiGe-on-insulator (SGOI) structure with the germanium (Ge) content of 25%. The electron mobility characteristics along the various current directions have been experimentally studied and compared to those of [100]- and [110]-surface unstrained-bulk MOSFETs. We have demonstrated, for the first time, that the electron mobility of [110] strained-SOI MOSFETs is enhanced, compared to that of [110] unstrained-bulk MOSFETs. The electron mobility enhancement depends on the current-flow directions, and the maximum enhancement factor amounts to 23% along the <001> direction. As a result, the electron mobility ratio of [110] strained-SOI MOSFETs to [100] universal mobility is 81% at maximum, whereas the ratio of [110] unstrained-bulk MOSFETs is only 66%. Therefore, [110] strained-SOI devices are also promising candidates for future high-performance CMOS.     

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.     

Monitoring hot-electron-induced degradation of floating-body SOIMOSFETs

A simple model relating the hot-electron-controlled device lifetime of floating-body SOI MOSFETs to the body voltage is discussed. The model is derived from the familiar relationship between the device lifetime and the substrate current of bulk MOSFETs, a relationship that cannot be measured directly in floating-body MOSFETs. The model, which allows quick estimation of the device lifetime from body-voltage measurements, is supported by measurements of hot-electron-induced degradation of floating-body SOI MOSFETs fabricated using SIMOX substrates     

A method to extract mobility degradation and total seriesresistance of fully-depleted SOI MOSFETs

Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed     

基于摄动法研究短沟道SOI MOSFET亚阈值特性

提出了一种新的方法对短沟道SOI MOSFETs亚阈区的二维表面势的解析模型进行了改进,即摄动法.由于在短沟道SOI MOSFETs中不仅需要计及不可动的电离杂质,而且需要考虑自由载流子的数量和分布的影响.利用摄动法求解非线性泊松方程可以得到短沟道SOI MOSFETs二维的表面势解析模型.通过与二维数值模拟器MEDICI模拟结果比较,证明了在亚阈区改进模型所得的结果比只计及不可动的电离杂质的SOI MOSFETs模型所得的结果吻合更好.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

An analytical model for fully depleted single gate SOI MOS transistors including lattice temperature effects

An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement.