基于忆阻器-CMOS晶体管的逻辑电路及其应用

针对传统组合逻辑电路存在的硬件资源利用率低和功耗高等问题,提出了一种基于忆阻器和CMOS晶体管的存算一体化组合逻辑电路设计方案。利用忆阻器存算一体、结构简单、与CMOS器件兼容等特性,减少了电路元器件数量。首先利用忆阻器的非易失性和阻变特性,设计忆阻与门、或门,结合CMOS晶体管实现与非门、或非门;然后,利用器件存算一体特性,提出了4R2T结构的异或门及同或门电路;最后,基于忆阻逻辑完备集设计了乘法器电路和图像加密电路,并采用LTspice验证电路功能正确性。结果表明,相比传统电路,所设计的乘法器电路元器件数量减少了50%,具有低功耗特性;所设计的图像加密电路具有良好的加密和解密效果,提升了运算效率。     

基于混合忆阻器-CMOS逻辑的全加器电路优化设计

将一种电压阈值型压控双极性忆阻器模型与CMOS反相器进行混合设计,实现了"与"、"或"、"与非"、"或非"基本逻辑门。通过构建"异或"逻辑门新结构,提出一种基于混合忆阻器-CMOS逻辑的全加器电路优化设计方案。最后,分析忆阻器参数β,V_t,R_(on)和R_(off)对电路运算速度和输出信号衰减幅度的影响,研究了该优化设计的电路功能和特性,经验证模拟仿真结果与理论分析结果具有较好的一致性。研究结果表明:全加器优化设计结构更简单,版图面积更小,所需忆阻器数量减少22.2%,CMOS反相器数量减少50%;增大参数β值可提高运算速度,增大忆阻值比率R_(off)/R_(on)可减小逻辑输出信号衰减度。     

忆阻数字逻辑电路设计

该文简要概述了忆阻器理论的提出、应用现状及其在电子技术领域发展的现状,介绍了忆阻器在数字逻辑电路设计中的重要意义,并结合惠普(HP)忆阻器的二值特性及其电路特性,对忆阻器在数字逻辑电路设计中的发展、趋势及可应用前景进行了综述,可为忆阻器在数字逻辑电路中的后续研究及相关应用提供一定的参考。     

基于忆阻器的乘法器电路设计

忆阻器作为一种非易失性的新型电路元件,在数字逻辑电路中具有良好的应用前景。目前,基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究,其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块,设计了一个2位二进制乘法器电路,另一种是结合新型的比例逻辑,即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较,并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器),相比于过去的忆阻乘法器,减少了大量晶体管的使用。     

基于忆阻器的组合逻辑电路设计

基于忆阻器的数字逻辑电路为探索先进的计算体系结构开辟了新的途径。在多种基于忆阻器的逻辑设计方法中,忆阻器比例逻辑(MRL)可以与传统CMOS工艺兼容制备出基本的门电路元件。简化了CMOS结构,仅单独使用NMOS管与忆阻器级联可以实现各种逻辑门单元。随后根据所提出的方案设计了编码器、解码器、全加器、乘法器等,并使用LTspice软件进行信号仿真,模拟结果与真值表完全一致。与传统的逻辑电路进行比较,该设计方案大量节省了元件数量,并且部分电路设计不需要为晶体管提供额外的独立电源,因此应用在更复杂的电路中可以大大节省芯片集成面积,为传统集成电路技术提供了一种有前途的替代方案。     

基于互补式忆阻器的多路复用器设计与实现

针对现有忆阻器逻辑设计方法所需忆阻器数量较大和操作步骤较多的问题,提出一种基于互补式忆阻器(complementary resistive switches,CRS)的灵活配置同行忆阻器的逻辑设计方法.通过对施加于CRS的高电压设置电压约束,更快速地实现布尔逻辑,并利用该方法实现了四种基本逻辑门,分别是与逻辑(AND)...     

基于FPGA的二值忆阻器仿真器研究及应用

基于FPGA的可重构性,提出了一种基于数字电路的二值忆阻器仿真器。与模拟电路忆阻器仿真器相比,所提出基于数字电路的忆阻器仿真器易于重新配置,与它所基于的数学模型表现出很好的匹配性,符合忆阻器仿真器所有要求的特点。实现了基于该仿真器的与门、或门、加法器及三人表决器。使用Altera Quartus II和ModelSim工具对仿真器功能和基于该仿真器实现的逻辑电路进行验证。给出所有设计电路的原理图、仿真结果和FPGA资源消耗。仿真结果表明,该二值忆阻器仿真器相比其他数字电路忆阻器仿真器具有更少的硬件资源消耗,更适合用于大规模忆阻器阵列研究。     

忆阻-CMOS混合模逆电路设计

模逆运算是加密算法中最复杂的运算,更是最关键的模块之一。忆阻器是替代现有的晶体管从而延续摩尔定律的有力竞争者。文中结合信息安全和忆阻器两个领域的研究现状,将忆阻蕴含机制应用于模逆电路设计,研究忆阻器应用于大规模数字电路中的可行性和适应性。首先,基于FPGA平台提出忆阻蕴含逻辑电路模型,进而实现了基础逻辑门和加法器等功能模块;再调用功能模块,成功设计出了基于二进制扩展的Euclidean算法的忆阻-CMOS混合模逆电路。经仿真与验证,模逆模块在200MHz的时钟下能正确地执行设计功能。     

基于忆阻器的感存算一体技术综述

忆阻器的低功耗、高响应、纳米级、非易失性等特性,在实现非冯·诺依曼计算架构中展现出巨大潜力。基于忆阻器的高密度横梁阵列可实现数据存储及并行计算一体的逻辑电路和类脑计算电路。此外,纳米传感器与忆阻器进一步集成,采集的信号直接送往忆阻器阵列进行运算和存储,感知、存储与计算一体化的芯片技术成为新的研究热点。该文对基于忆阻器的存算一体技术、感存算一体技术的研究现状进行综述,并给出研究前景展望。     

基于忆阻器的感存算一体技术综述

忆阻器的低功耗、高响应、纳米级、非易失性等特性,在实现非冯·诺依曼计算架构中展现出巨大潜力.基于忆阻器的高密度横梁阵列可实现数据存储及并行计算一体的逻辑电路和类脑计算电路.此外,纳米传感器与忆阻器进一步集成,采集的信号直接送往忆阻器阵列进行运算和存储,感知、存储与计算一体化的芯片技术成为新的研究热点.该文对基于忆阻器的存算一体技术、感存算一体技术的研究现状进行综述,并给出研究前景展望.     

Domino logic with variable threshold voltage keeper

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.     

FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.     

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

In this paper, we propose a novel full adder design using as few as ten transistors per bit. Compared with other low-gate-count full adder designs using pass transistor logic, the proposed design features lower operating voltage, higher computing speed and lower energy (power delay product) operation. The design adopts inverter buffered xor/xnor designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from operating in low supply voltage or cascading directly without extra buffering. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both dc andperformances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35-mum process models, indicate that the proposed design has the lowest working V_dd and highest working frequency among all designs using ten transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases     

Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic

Dynamic logic is susceptible to noise, especially in the ultra-deep submicrometer dual threshold voltage technology. When the dual threshold voltage is applied to the domino logic, noise immunity must be carefully considered since the significant subthreshold current of the low threshold voltage transistor makes the dynamic node much more susceptible to noise. In the first part of this paper, we introduce a new keeper transistor sizing method to determine the optimal keeper transistor size in terms of speed, power, and noise immunity. With the use of data obtained by presimulation, it is unnecessary to simulate all the design corners corresponding to the feasible NMOS evaluation transistor size ranges to find the optimal keeper transistor size. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all the domino logic gates. In the second part of this paper, we propose a new dual threshold voltage domino logic synthesis with the keeper transistor sizing to minimize the power consumption while meeting delay and noise constraints. With the optimal keeper transistor size determined by the proposed keeper transistor sizing method, the dual threshold voltage assignment to domino logic can be simplified to the discrete threshold voltage selection. Experimental results for ISCAS85 benchmark circuits show significant savings on leakage power and active power.     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

Design and simulation of novel TLG–SET based configurable logic cells

Single electron tunneling circuits seem to be promising candidates as basic circuit elements of the next generation ultra-dense VLSI and ULSI circuits for their ultra-low power consumption, ultra-small size, and rich functionality. In this paper, design and simulation of novel configurable logic cells (CLCs) using single electron tunneling (SET) technology based threshold logic gate (TLG) are presented. The proposed CLC can realize all Boolean logic functions by configuring the control bits without changing the structure of the circuit and the parameters of TLG–SET based design. The logic operation of the circuit is simulated using Monte Carlo simulation. According to the simulation results, the circuit operation based on the transfer of single electrons between adjacent islands is stable.     

A static random-access memory with normally-off-type Schottky barrier FET's

A large-scale integrated memory with lower power consumption and high operating speed has been developed and evaluated. A fully decoded 256-b static random-access memory chip was fabricated by using the Enhancement-type Schottky Barrier gate FET's, having a threshold voltage of 0.1 V, obtained by ion-implantation. The memory chip was successfully operated with an access time of less than 150 ns, and with active power consumption of 15 mW/chip. A single power supply of -1.3 V and current mode logic input levels are additional features of the memory chip.     

Charge recycling differential logic (CRDL) for low powerapplication

A novel logic family, called charge recycling differential logic (CRDL), has been proposed and analyzed. CRDL reduces power consumption by utilizing a charge recycling technique with the speed comparable to those of conventional dynamic logic circuits. It has an additional benefit of improved noise margin due to inherently static operation. The noise margin problem of true single-phase-clock latch (TSPC) is also eliminated when a CRDL logic circuit is connected to it. Two swing-suppressed-input latches (SSILs), which are introduced for use with CRDL, have better performance than the conventional transmission gate latch. Moreover, a pipeline configuration with CRDL in a true two-phase clocking scheme shows completely race-free operation with no constraints on logic composition. Eight-bit Manchester carry chains and full adders were fabricated using a 0.8 μm single-poly double-metal n-well CMOS technology to verify the relative performance of the proposed logic family. The measurement results indicate that about 16-48% improvements in power-delay product are obtained compared with differential cascode voltage switch (DCVS) logic     

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.