适用于TIADC的高精度时间失配误差校准算法

设计了一种适用于TIADC的高精度时间失配误差校准算法。基于相邻通道信号互相关原理,对相邻通道的输出信号作相关运算来估计时间失配误差,再利用基于泰勒级数展开的高阶误差校准方法进行误差校正。误差估计模块与校准模块构成一个反馈环路,可以实现误差的实时跟踪和校正。校准算法行为级仿真结果表明,在12位1 GHz四通道的TIADC中,当输入信号归一化频率f_in/f_s=0.477 1时,校准后系统的ENOB提高到11.85位,SNR提高了43 dB以上,校准效果明显。相比已有的校准算法,该校准算法具有更高的校准精度,不受通道数的限制,结构更简单,且在整个奈奎斯特频率范围内都适用,非常适合工程应用。     

基于导数相乘的TIADC时间失配误差校准算法

提出了一种校准时间交织模数转换器(TIADC)时间失配误差的全数字后台算法。该算法利用信号与其导数正交的特性来估算时间失配误差相关量,采用最小均方(LMS)迭代算法估算时间失配误差值。该算法不需要参考通道,硬件消耗很低,可以校准多频信号,实现宽带宽输入。提出的变步长LMS迭代算法提高了时间失配误差的收敛速度,保证了误差校准的实时性。基于FPGA验证平台,建立了四通道8 bit 1 GHz TIADC的时间失配误差模型。结果表明,当输入信号归一化频率f_in/f_s为0.414时,采用该算法校准后的ENOB从5.58 bit提高到7.75 bit,SFDR从38.64 dB提高到67.51 dB。     

带单bit参考通道的TIADC时间失配校准

提出了一种带单bit参考通道的校准算法,用于校准时间交织模数转换器(Time-interleaved analog-todigital converter,TIADC)的时间失配误差。该算法引入一条单bit的参考通道,其输出与TIADC子通道的输出进行相关运算获得误差信息,然后反馈到多相时钟产生器,形成反馈环路,达到校准的目的。该算法只引入了一条单bit的参考通道,硬件消耗低,对输入信号的频率没有限制,且可以扩展到任意通道数。算法应用于一个4通道12bits的TIADC,当输入信号归一化频率fin/fs=0.484 8时,MATLAB仿真结果表明,经本算法校准后SNR从14.39dB提高到73.92dB,证明了该校准方案的有效性。     

基于参考信号注入的TIADC时间失配校准算法

提出了一种基于参考信号注入的TIADC时间失配后台校准算法。该校准算法统计通道间的参考信号过零点个数,比较相邻2个峰值的大小,计算得出误差系数,并将该误差系数反馈回时钟采样控制单元进行校正。采用Simulink软件建立12位5通道TIADC模型,仿真结果表明,当fin/fs≈0.040 3时,有效位数从8.1位提升到11.8位,验证了算法的可行性。算法中的时间失配误差提取与TIADC分开,并行处理,保证了输入信号在整个奈奎斯特频率范围内不受影响。该校准算法消耗资源少,易于硬件实现。     

针对时间交织采样的后台自适应频域校准技术

针对高速双通道时间交织采样(Time-interleaved Analog-to-Digital Converter, TIADC)系统通道失配的问题,提出了一种后台自适应频域校准技术。该技术采用数字混频+低通滤波技术,将失配镜像点搬移至零频,并形成I/Q复数信号;然后基于信号统计学进行校准系数计算,并利用该系数完成共轭对消校准;最后将校准后信号通过数字混频搬移回原始频率,完成整个校准过程。进一步提出了基于FPGA/ASIC的算法实现电路。经实物测试验证,在6 Gsample/s双通道TIADC系统中,该技术能够优化失配比达33.3 dBc以上,失配优化程度高,同时具有全流水实时后台处理特性,且不需要增加额外系统资源。     

时间交织ADC时间失配后台数字校准算法

提出了一种数字后台校准算法,用于校准时间交织模数转换器(Time-Interleaved Analog-to-Digital Converter,TIADC)的时间失配误差。该算法是基于对输入信号统计的思想,在后台通过分析输入信号的统计特性获得误差信息,再反馈到多相时钟产生器,形成反馈环路,达到校准的目的。该算法硬件消耗小,对输入信号的频率没有限制,可以扩展到任意通道数。对于一个8通道12位TIADC,当输入信号频率fin/fs = 0.487时,MATLAB仿真结果表明,采用该算法校准后,SNR从校准前的33.8 dB提高到74.0 dB,证明了该校准算法的有效性。     

通道间差值统计的TIADC时序误差校准方法

利用某相邻采样通道的绝对差值与全部相邻通道的平均绝对差值应保持一致的原理,对TIADC的采样时序误差进行估计,再利用泰勒展开的方法实现误差补偿。在校准过程中,将误差估计模块和误差补偿模块组成一个自适应的环路,实现了采样时序误差的实时校准。全部校准过程在纯数字域中完成。这种纯数字后处理式的误差估计方法简单有效,3阶泰勒误差补偿方法的补偿效果良好。基于MATLAB建立了4通道TIADC的时序失配误差校准模型,验证了该校准方法的正确性和有效性。结果表明,通道间的时序误差为1%~2%,在输入归一化频率fin/fs为0.397时,校准后系统的SNR由原来的18.85 dB提高到73.31 dB。     

一种基于LMS算法的天线阵通道失配校正技术及VLSI实现

天线阵各通道之间的通道失配（幅相特性不一致）会严重影响阵列信号处理的性能[1,2],为此在进行阵列信号处理前必须对各通道的幅相特性进行均衡.本文针对天线阵通道之间与频率无关的恒定通道失配问题,提出了一种基于LMS好地校正与频率无关的通道失配.本算法的易于工程实现的通道校正技术.计算机仿真结果表明,采用这种技术可以很文最后还给出了该算法在VLSI（超大规模集成电路）平台上的实现结构.     

基于改进微分器设计的TIADC增益误差校准算法

针对传统微分器在处理TIADC系统中存在的增益误差时设计复杂、硬件资源消耗大而且校准算法校准频率范围比较局限,提出了一种利用Hilbert滤波器对传统微分器进行改进并构建校准算法,算法的Matlab仿真分析表明,在输入信号归一化频率为0.8546( )时,由误差引起的杂散被有效滤除,通过对SNR参数指标进行比较,由18.3dB提高到了68.5dB。相比传统结构算法,该算法可将校准带宽拓展至第一奈奎斯特频带以外,实现宽频带范围信号的校准,在实际应用过程中很大参考价值。     

Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs

Bandwidth mismatch between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) causes undesirable distortions in the output spectrum. To reduce these undesired spectral components, methods are needed to estimate and correct the mismatch. In this paper, we introduce a hybrid filter-bank model of a two-channel time-interleaved ADC. The model allows the development of digital domain estimation and correction techniques. The estimation method is a semiblind estimation technique where a test tone of small amplitude is injected just below the half sampling frequency and is used to estimate the bandwidth mismatch without affecting the normal ADC operation. The estimation procedure relies on an adaptive filtering structure with three fixed relatively short finite-impulse response (FIR) filters and a single adjustable tap representing the estimated relative bandwidth mismatch of the two S/Hs. The correction method removes the first-order effects of S/H mismatches. It only requires a first-order fixed IIR filter and two fixed FIR filters. Simulations demonstrate the effectiveness of the proposed estimation and correction techniques.     

一种时间交织ADC采样时间误差校正方法

提出了一种用于时间交织模数转换器(TIADC)通道间采样时间误差的校正算法。该算法是基于参考通道的后台校正算法。通过比较参考通道与带校准通道的输出差异提取出采样误差信息,并通过负反馈逻辑进行校准。该算法的校正模块硬件消耗低,可支持包括完全随机输入信号的多种类型输入信号。将该校正算法应用于一个4 GHz、8 bit四通道TIADC,后仿真结果表明,当输入信号接近奈奎斯特频率、存在其他非理想因素的条件下,该算法能将通道间采样时间误差相关的频谱尖峰抑制到35 dB。     

Estiamtion and Correction of Mismatch Errors in Time-Interleaved ADCs

In data acquisition systems, with help of time-interleaved analog-to-digital converter (TIADC) architecture, the maximum sample rate of the whole system can be increased efficiently. However, inevitable offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the sampling performance. In order to develop the mismatched TIADC structure, this paper first proposes a new time-domain algorithm to estimate the three aforementioned mismatch errors, and then puts forward a calibration method to calibrate the mismatch errors. Finally, numerical simulations are presented to verify the proposed estimation and calibration algorithm.     

Multichannel Time Skew Calibration for Time-Interleaved ADCs Using Clock Signal

Time skew in time-interleaved ADCs (TI-ADCs) degrades the system’s linearity significantly.To address this problem, a time skew calibration method is proposed here that employs the divided clock signal as calibration signal. The divided squared clock signal containing a limited number of harmonics is demonstrated to be effective to extract the time skew, which is detected by comparing the estimated mean value of the product of two adjacent channels’ signals without extra reference ADC channel. The extracted time skew is subsequently compensated by a capacitor array-based digitally controlled delay block. Simulation results of a 4-channel 1GS/s 12-bit TI-ADC design demonstrated that the proposed calibration technique improved the spurious-free dynamic range of the ADC to 77 dB with a digitally controlled delay block that offers a time tuning resolution of 0.2 ps.     

Linear LMS Compensation for Timing Mismatch in Time-Interleaved ADCs

The time-interleaved architecture permits the implementation of high-frequency analog-to-digital converters (ADCs) by multiplexing the output of several time-shifted low-frequency ADCs. An issue in the design of a time-interleaved ADC is the compensation of timing mismatch, which is the difference between the ideal and real sampling instants. In this paper, we propose a compensation method that, as opposite to existing approaches, does not assume that the input signal is band limited but assumes instead that it has a stationary known power spectrum. The compensation is then designed in a statistically optimal sense. This largely reduces the compensation order required to achieve a given reconstruction accuracy. Also, under the band-limited assumption, the proposed method achieves perfect reconstruction if no constraints are imposed on the order of the compensation. Simulation results show that a rough estimate of the input spectrum can be used without much performance loss, showing that an accurate knowledge of the input spectrum is not necessarily required.      

Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs

In this paper, we describe a blind calibration method for timing mismatches in a four-channel time-interleaved analog-to-digital converter (ADC). The proposed method requires that the input signal should be slightly oversampled. This ensures that there exists a frequency band around the zero frequency where the Fourier transforms of the four ADC subchannels contain only three alias components, instead of four. Then the matrix power spectral density (PSD) of the ADC subchannels is rank deficient over this frequency band. Accordingly, when the timing offsets are known, we can construct a filter bank that nulls the vector signal at the ADC outputs. We employ a parametrization of this filter bank to develop an adaptive null steering algorithm for estimating the ADC timing offsets. The null steering filter bank employs seven fixed finite-impulse response filters and three unknown timing offset parameters which are estimated by using an adaptive stochastic gradient technique. A convergence analysis is presented for the blind calibration method. Numerical simulations for a bandlimited white noise input and for inputs containing several sinusoidal components demonstrate the effectiveness of the proposed technique     

时间交叉模数转换系统的时间失配补偿

时间交叉模数转换结构是提高模数转换系统采样率的一种有效途径。由于制造工艺的局限和布线的差异,这种结构会引入通道失配而限制系统的性能。通道失配包括偏置失配、增益失配和时间失配。文中提出了一种基于快速傅里叶变换（Fast Fourier Transform,FFT）计算时间失配并采用有限冲激响应（Finite Impusle Response,FIR）滤波器对它进行补偿的方法,并通过Matlab仿真验证了算法的有效性和可行性。     

A Filter Bank Mismatch Calibration Technique for Frequency-Interleaved ADCs

The filter bank mismatch of analog analysis filters in frequency-interleaved ADCs (FI-ADCs) degrades the system’s spurious-free dynamic range (SFDR) significantly. In this paper, a calibration approach for compensating such mismatch is presented. By modeling the parameter mismatches in the analysis filters, the filter bank mismatch compensation is divided into a coarse trimming mode and a fine-tuning mode. After the coarse trimming mode by trimming the resistors and capacitors in analog domain, the fine-tuning mode by updating coefficients of synthesis filters is further carried out in digital domain to achieve high-precision calibration. A design example of 10 GS/s 8-bit four-channel FI-ADC is built in MATLAB. The simulation results show that 25-tap synthesis filters could satisfy the reconstruction requirement of 8-bit ADC. The proposed calibration technique improves the SFDR to 51 dB, compensating the filter mismatch effectively.     

An On-Line Calibration Technique for Mismatch Errors in High-Speed DACs

In this paper a novel online calibration technique for high-speed DACs is presented. The approach consists of two elements. The first element is the use of a redundant signed digit (RSD) scheme for the selection of the current sources. This enables a fully digital correction. The second element consists of an adaptive estimation of the correction terms by an LMS algorithm. For this purpose the DAC output signal is low-pass filtered and digitized by an accurate but low-speed calibration ADC. By replicating this analog signal path in the digital domain, the errors can be calculated and used to update the correction weights. The dynamic behavior and the accuracy of the adaptive calibration loop are analyzed both theoretically and through computer simulations, and it is shown that this way a greatly improved accuracy can be obtained.