Integrated interconnect networks for RF switch matrix applications

In this paper, two new types of integrated RF interconnect networks are presented. The circuits are printed on double-sided alumina substrates, eliminating the need to use multilayer manufacturing technology. The interconnect networks employ finite ground coplanar lines and vertical transitions and can be easily integrated with semiconductor and microelectromechanical-systems switches. A wide-band 3/spl times/3 interconnect network utilizing single and double three-via vertical transitions is investigated theoretically and experimentally. The measured results show a return loss of -20dB and an isolation of better than -40dB up to 30 GHz. A vialess double-sided interconnect network is also studied and optimized for satellite Ku-band applications. This type of interconnect network uses a process requiring only front and back pattern metallization. The measured results indicate a return loss of better than -17dB and an isolation of better than -45dB.     

A multifunctional high-speed switch element for ATM applications

Describes a one-chip 16*8 switch element SE16/8 based upon the shared buffered concept. The device's data inputs/outputs work at a data rate of 175.8 Mb/s, and its central clock inputs at a frequency of 351.6 MHz. To achieve the high system flexibility demanded, the circuit is equipped with many powerful functions: bit-phase alignment, a priority handling feature, a logic circuit, and a RAM self-test option. The SE16/8 was designed in a state-of-the-art 1- mu m CMOS technology comprising 770000 transistors on a chip area of 216 mm/sup 2/. It was packed in a frequency-matched ceramic multilayer quad flat package to cope with the high power (3 W) and speed requirements. The first switching modules built up with the SE 16/8 have already shown the functional superiority of the device presented.<>     

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.     

A new meshing criterion for the equivalent thermal analysis of GaAs PHEMT MMICs

In this paper, a new meshing criterion for the equivalent thermal analysis of GaAs PHEMT MMICs (Monolithic microwave integrated circuit) is proposed. Based on the meshing criterion, an equivalent thermal model of GaAs PHEMTs with remarkably reduced mesh complexity is established, and the simplification of both layout pattern and vias of MMICs are performed. Theoretical analysis is applied for the calibration of the equivalent thermal model. Assisted by the meshing criterion, chip-level simulators are capable to obtain the peak temperature of MMICs without using averaging approximations, and achieve considerably high simulation accuracy. As examples, two MMIC power amplifiers are designed and implemented using GaAs PHEMT process. Thermal simulation and measurement results obtained with ANSYS ICEPAK and infrared thermography, respectively, show high consistency. The proposed meshing criterion can be applied to improve the accuracy of thermal analysis of MMICs, and the obtained precise peak temperature can be used to effectively assess the power threshold of the designed amplifiers in reliability tests.     

Broad-band SiGe MMICs for phased-array radar applications

This paper reports the performances of several broad-band monolithic SiGe monolithic microwave integrated circuits (MMICs) suitable for phased-array radar applications. The amplitude and phase control MMIC designs are based on an optimized SiGe p-i-n diode offered by the IBM 5HP SiGe foundry process. Utilizing this diode, several control circuitries including a broad-band (1-20-GHz) monolithic single-pole double-throw switch, a five-port transfer switch, a 6-bit phase shifter, and a 5-bit attenuator, all operating over 7-11 GHz, are designed. Also, the design and performance of an SiGe heterojunction bipolar transistor variable-gain cascode amplifier that combines the functionality of an amplifier and an attenuator into one MMIC is described.     

AlAs etch-stop layers for InGaAlAs/InP heterostructure devices andcircuits

Wet chemical etching solutions were developed that allow the selective etching of InP lattice-matched InGaAs and InAlAs compounds using thin pseudomorphic AlAs layers as etch stop. Several dicarboxylic acids were found that allow the etching of indium compounds. The best results were obtained for etchants consisting of succinic acid, ammonia, and hydrogen peroxide. The etch rate in In_0.53Ga_0.47 As is found to be over 1000 times the etch rate of AlAs, while the etch rate of In_0.52Ga_0.48As is over 500 times that of the AlAs. The dependences of the succinic acid based etch on p H and hydrogen concentration were also studied. Buffered HF can be used to remove the AlAs stop layer, while it does not etch InGaAlAs to any significant degree     

Laser-activated p-i-n diode switch for RF application

Results obtained utilizing an optically activated RF switch in the 2-30-MHz range demonstrate the advantages in optically controlled high-power switches from HF to millimeter wave. Testing of a 0.25-mm-thick p-i-n device activated with 116-W peak optical power from a two-dimensional laser array in a 50-Ω system shows isolation between 20.8 and 49 dB, and an average insertion loss of 0.38 dB when measured between 2.5 and 30 MHz     

Detecting signal-overshoots for reliability analysis in high-speed system-on-chips

The rising level of complexity and speed of SoC makes it increasingly vital to test adequately the system for signal integrity. Voltage overshoot is one of the integrity factors that has not been sufficiently addressed for the purpose of testing and reliability. Overshoots are known to inject hot-carriers into the gate oxide and cause permanent degradation of MOSFET transistors' performance. This performance degradation creates a serious reliability concern. Unfortunately, accurate parasitic extraction and simulation to detect the interconnect problems is very time consuming and very sensitive to the circuit characteristics and thus is not practical for large SoC. This paper presents a built-in chip methodology to detect and measure the signal overshoots occurring on the interconnects of high-speed system-on-chips. This built-in test strategy does not require external probing or signal waveform monitoring. Instead, the overshoot detector cells monitor signals received by a core (e.g. from the system bus) and record the occurrence of overshoots over a period of operation. The overshoot information accumulated by these cells can be compressed and scanned out efficiently And inexpensively for final quality grading, reliability analysis and diagnosis.     

CMOS high-speed dual-modulus frequency divider for RF frequencysynthesis

The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presented. Compared to other designs fabricated with comparable CMOS technologies, this architecture has a better potential for high-speed operation. The circuit consumes less power than previously reported CMOS circuits, and it approaches the performance previously achieved only by bipolar or GaAs devices. The proposed circuit uses level-triggered differential logic to create an input-frequency-entrained oscillator performing a dual-modulus frequency division. In addition to high-speed and low-power consumption, the divider has a low-input signal level requirement which facilitates its incorporation into RF applications. Fabricated with a 1.2-μm 5-V CMOS technology, the divider operates up to 1.5 GHz, consuming 13.15 mW, and requiring less than 100 mV rms input amplitude     

用于移动通信的砷化镓高频PHEMT小功率晶体管

砷化镓PHEMT功率器件具有工作频率高，输出功率密度大，效率高，功率增益高等特点，我们研制的0．5μm栅长GaAsPHEMT小功率晶体管，栅宽1mm，直流跨导250ms/mm，栅漏反向击穿电压大于13V，在20GHz下最大可用增益为8dB，X波段输出功率为0．8W／mm，可应用于22GHz以下的窄带功率放大器和18GHz以下的宽带功率放大器。     

A photonic knockout switch for high-speed packet networks

A high-performance packet switch is discussed which uses a photonic interconnect fabric to route very-wideband data packets from input to output. Packet contention is accomplished using a much slower electronic controller, based on the knockout principle operating in parallel with the optical interconnect. Specifically, the use of a wavelength-division-multiplex fabric whereby high-speed (2-4 Gb/s) packets are regenerated before modulating a single-frequency laser at each switch input. The optical signals from various inputs are summed in a star coupler and then broadcast to the different coupler outputs. Each coupler is equipped with a small number (L) of tunable receivers arranged in a parallel manner, each preceded by a power splitter so that up to L simultaneous packets can be received by each output. The L packets so received are stored in an L-input one-output first-in first-out (FIFO) buffer so that the FIFO packet sequence is always guaranteed. Not only does this architecture achieve the best delay-throughput performance, but, remarkably, modularity is such that the optical complexity grows linearly with the number of switch ports./     

Large-area oxidation of AlAs layers for dielectric stacks and thick buried oxides

The wet oxidation of AlAs and AlGaAs has been limited to relatively small lateral dimensions and relatively thin layers. Approaches are described to extend the oxide dimensions both horizontally and vertically, creating large-area and thick buried oxides. Two types of large-area structures are examined: dielectric stacks with thin buried oxides and semiconductor-on-insulator structures with thick buried oxides. Low Al-content AlGaAs layers with low oxidation rates are used as the high-index layers in large-area dielectric-stack structures. High Al-content AlGaAs layers with low volume contraction are used to create stable, thick buried oxides with millimeter-scale areas.     

Analogue switch for very low-voltage applications

A new analogue switch suitable for operation at very low-voltage supply in a standard CMOS technology is presented. The proposed switch is based on 'quasi-floating-gate' transistors and has a simple and compact structure. For illustrative purposes, two sample-and-hold circuits operating from a single supply voltage close to the threshold voltage of a transistor, and using the proposed technique, are presented. Experimental results obtained from prototypes in a 1.5 /spl mu/m CMOS technology are provided.     

Performance evaluation of a high-speed ATM switch with multiplecommon memories

We consider a common-memory (CM) type N × N ATM switch, where CM block consists of K (K ⩾ N) separated submemories. We propose an address assignment algorithm to avoid input/output contentions so that we can have the read/write speed of submemories as low as the interface (input/output) port speed. Taking a replication-at-sending approach to multicast, we pursue memory efficiency and maximum throughput. We develop an analytical model to evaluate the system in terms of cell loss ratio and average delay time. In the analysis, we take into account two loss factors causing losses of incoming cells: (1) the failure of scheduling to avoid the input/output contentions and (2) overflow in the CM block. The first factor is dominating and can be significantly reduced by increasing K. From our analytical results compared with simulations, it is observed that we can take K ≈ 3N as a guide of system design     

无线局域网射频前端器件的选择--化系统性能和电流消耗

一个802．11WLAN无线电接收装置的前端一般由滤波器、开关、功率放大器(PA)、平衡一不平衡转换器、分立器件组成,有时还包括低噪声放大器(LNA)。应细心选择这些器件和他们的结构,以满足、优化在性能、法规、电流消耗和成本方面的要求。     

MMIC用多层磁膜电感研究

采用磁控溅射生长磁膜工艺,结合BCB(苯并环丁烯)平坦化技术,首次制作了"金属线圈/磁膜/金属线圈(M/F/M)"和"磁膜/金属线圈/磁膜/金属线圈(F/M/F/M)"两种结构的多层磁膜电感,整个工艺与标准MMIC工艺兼容.在2 GHz处,"金属线圈/磁膜/金属线圈"结构电感的电感量为7.5 nH,品质因数为7.17,...     

Analysis of RF MEMS switch packaging Process for yield improvement

Radio frequency microelectro-mechanical systems (RF MEMS) switches offer significant performance advantages in high-frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320degC. The assembled packages were then attached to a printed circuit board at 220degC. During the process, some switches failed due to electrical shorting. Interestingly, more failures were observed at the lower temperature of 220degC rather than 320degC. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance     

Thermal solutions for discrete and wafer-level RF MEMS switch packages

In discrete radio frequency (RF) microelectromechanical systems (MEMS) packages, MEMS devices were fabricated on silicon or gallium arsenide (GaAs) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 /spl Omega/ exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities. In this paper, thermal analysis has been performed to study the heat dissipation at the switch contact area. The goal is to control the "hot spots" and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials has been considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and low-temperature cofired ceramic (LTCC) have been studied. Thermal experiments have been conducted to measure the temperature at the contact area and its vicinity as a function of dc and RF powers. Several solutions in material selection and package configurations have been explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity. For discrete MEMS packages, placing the die inside a copper cavity on the substrate provides significant heat dissipation. For wafer-level packages, thin diamond coatings on the substrate could reduce the hot-spot temperature considerably.     

Crosstalk between finite ground coplanar waveguides over polyimide layers for 3-D MMICs on Si substrates

Finite-ground coplanar (FGC) waveguide lines on top of polyimide layers are frequently used to construct three-dimensional Si-SiGe monolithic microwave/millimeter-wave integrated circuits on silicon substrates. Requirements for high-density, low-cost, and compact RF front ends on silicon can lead, however, to high crosstalk between FGC lines and overall circuit performance degradation. This paper presents theoretical and experimental results and associated design guidelines for FGC line coupling on both highand low-resistivity silicon wafers with a polyimide overlay. It is shown that a gap as small as 6 /spl mu/m between two adjacent FGC lines can reduce crosstalk by at least 10 dB, that the nature of the coupling mechanism is not the same as with microstrip lines on polyimide layers, and that the coupling is not dependent on the Si resistivity. With careful layout design, isolation values of better than -30 dB can be achieved up to very high frequencies (50 GHz).