High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

Nonvolatile-Memory Characteristics of $hbox{AlO}^{-}$ -Implanted $hbox{Al}_{2}hbox{O}_{3}$

The nonvolatile-memory (NVM) characteristics of $hbox{AlO}^{-}$ -implanted $hbox{Al}_{2}hbox{O}_{3}$ structures are reported and shown to exhibit promising behaviors, including fast program/erase speeds and high-temperature data retention. Photoconductivity spectra show the existence of two dominant trap levels, located at around 2 and 4 eV below the conduction band minimum of $hbox{Al}_{2}hbox{O}_{3}$, and our calculations show that these levels are likely attributed to the defects in the $hbox{Al}_{2}hbox{O}_{3}$, such as the Al–O divacancy. The relative concentrations of these defects vary with the implant fluence and are shown to explain the NVM characteristics of the samples irradiated to different fluences.      

Lattice-Mismatched $hbox{In}_{0.4}hbox{Ga}_{0.6} hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel n-MOSFETs

We report the first demonstration of a strained $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ channel n-MOSFET featuring in situ doped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ source/drain (S/D) regions. The in situ silicondoped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ S/D was formed by a recess etch and a selective epitaxy of $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ in the S/D by metal–organic chemical vapor deposition. A lattice mismatch of $sim$0.9% between $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and $hbox{In}_{0.4} hbox{Ga}_{0.6}hbox{As}$ S/D gives rise to lateral tensile strain and vertical compressive strain in the $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ channel region. In addition, the in situ Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.      

Scaling Properties of $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ Core–Shell Nanowire Field-Effect Transistors

We demonstrate the fabrication of high-performance $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ core–shell nanowire (NW) field-effect transistors with highly doped source (S) and drain (D) and systematically investigate their scaling properties. Highly doped S and D regions are realized by low-energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the NW resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and on/off current ratio.      

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

Low-Voltage and High-Speed Operations of 30-nm-Gate Pseudomorphic $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}/hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$ HEMTs Under Cryogenic Conditions

In this letter, we fabricated 30-nm-gate pseudomorphic In_0.52 Al_0.48As/In_0.7Ga_0.3As HEMTs with multilayer cap structures to reduce source and drain parasitic resistances; we measured their dc and radio-frequency characteristics at 300, 77, and 16 K under various bias conditions. The maximum cutoff frequency fT was 498 GHz at 300 K and 577 GHz at 77 K. The maximum fT exceeded 600 GHz at 16 K. Even at a drain-source voltage V _ds of 0.4 V, we obtained an fT of 500 GHz at 16 K. This indicates that cryogenic HEMTs are favorable for low-voltage and high-speed operations. Furthermore, the present 30-nm-gate HEMTs at 300 K show almost the same fT values at the same dc-power dissipation as compared to 85-nm-gate InSb-channel HEMTs. The improvement of the maximum-oscillation-frequency f _max values was also observed at 77 and 16 K.     

Improvement of On–Off-Current Ratio in $ hbox{TiO}_{rm x}$ Active-Channel TFTs Using $hbox{N}_{2} hbox{O}$ Plasma Treatment

Without sacrificing the on-current in the transfer characteristics, we have successfully reduced the off-current part by the optimal $hbox{N}_{2}hbox{O}$ plasma treatment to improve the on–off-current ratio in n-type titanium oxide $( hbox{TiO}_{rm x})$ active-channel thin-film transistors. While the high-power (275 W) $hbox{N}_{2}hbox{O}$ plasma treatment oxidizes the whole $hbox{TiO}_{rm x}$ channel and results in the reduction of both on- and off-current, the optimized low-power (150 W) process makes the selective oxidation of the top portion in the channel and reduces only the off-current significantly. Increase in on–off ratio by almost five orders of magnitude is achieved without change in on-current by using the presented method.      

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.     

ZnO Nanowire and $hbox{WS}_{2}$ Nanotube Electronics

In this paper, we report on the synthesis and applications of semiconducting nanostructures. Nanostructures of interest were zinc oxide (ZnO) nanowires and tungsten disulfide $(hbox{WS}_{2})$ nanotubes where transistors/phototransistors and photovoltaic (PV) energy conversion cells have been fabricated. ZnO nanowires were grown with both high- and low-temperature approaches, depending on the application. Individual ZnO nanowire side-gated transistors revealed excellent performance with a field-effect mobility of 928 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. ZnO networks were proposed for large-area macroelectronic devices as a less lithographically intense alternative to individual nanowire transistors where mobility values in excess of 20 $ hbox{cm}^{2}/hbox{V} cdot hbox{s}$ have been achieved. Flexible PV devices utilizing ZnO nanowires as electron acceptors and for photoinduced charge separation and transport have been presented. Phototransistors were fabricated using individual $hbox{WS}_{2}$ nanotubes, where clear sensitivity to visible light has been observed. The results presented here simply reveal the potential use of inorganic nanowires/tubes for various optoelectronic devices.      

Resistive-Switching Characteristics of $hbox{Al}/ hbox{Pr}_{0.7}hbox{Ca}_{0.3}hbox{MnO}_{3}$ for Nonvolatile Memory Applications

A systematic study on the switching mechanism of an $hbox{Al}/ hbox{Pr}_{0.7}hbox{Ca}_{0.3}hbox{MnO}_{3}$ (PCMO) device was performed. A polycrystalline PCMO film was deposited using a conventional sputtering method. A thin Al layer was introduced to induce a reaction with the PCMO, forming aluminum oxide $(hbox{AlO}_{x})$. Transmission electron microscopy analysis of the interface between Al and PCMO showed that resistive switching was governed by the formation and dissolution of $hbox{AlO}_{x}$. Some basic memory characteristics, such as good cycle endurance and data retention of up to $hbox{10}^{4}$ s at 125 $^{circ}hbox{C}$, were also obtained. It also showed excellent switching uniformity and high device yield.      

A Monte Carlo Study of $hbox{Hg}_{0.7}hbox{Cd}_{0.3}hbox{Te}$ e-APD

A simple Monte Carlo model is developed for understanding the multiplication process in HgCdTe infrared avalanche photodiodes and the impact of physical and technological parameters. A good agreement is achieved between simulations and experimental measurements of gain and excess noise factor. In both cases, an exponential gain and extremely low noise—$F sim hbox{1}$ for multiplication gains up to 1000—were observed on 5.1-$muhbox{m}$ cutoff devices at 77 K, indicative of a single carrier impact ionization. A comparison study is presented to explain the effect of different combinations of scattering processes on the avalanche phenomenon in HgCdTe.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

$hbox{VO}_{2}$ Thin-Film Varistor Based on Metal-Insulator Transition

For electronic applications, we have fabricated VO₂ thin-film variable resistors (varistors) using metal-insulator transition regarded as the abrupt current jump. The increase of the number of parallel stripe patterns in the varistor leads to the increase in current below a current-jump voltage, which endures a high surge voltage with high current and short rising time. Electrostatic discharge (ESD) experiments show that the varistic coefficient of 500 is larger than 30-80, which is known for commercial ZnO varistors. In overvoltage-protection tests applying high ESD voltages up to 3.3 kV to a varistor, the maximum response voltage is lower than 200 V at an ESD voltage of 1600 V, and the electronic response time is less than 20 ns. This is sufficient to protect a device perfectly.     

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFET

We report the experimental demonstration of deep-submicrometer inversion-mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFETs with ALD high- $k$ $hbox{Al}_{2}hbox{O}_{3}$ as gate dielectric. In this letter, n-channel MOSFETs with 100–200-nm-long gates have been fabricated. At a supply voltage of 0.8 V, the fabricated devices with 200–130-nm-long gates exhibit drain currents of 232–440 $muhbox{A}/muhbox{m}$ and transconductances of 538–705 $muhbox{S}/muhbox{m}$. The 100-nm device has a drain current of 801 $muhbox{A}/muhbox{m}$ and a transconductance of 940 $muhbox{S}/muhbox{m}$. However, the device cannot be pinched off due to severe short-channel effect. Important scaling metrics, such as on/off current ratio, subthreshold swing, and drain-induced barrier lowering, are presented, and their relations to the short-channel effect are discussed.      

The $hbox{Pd/TiO}_{2}$/ $hbox{n}$-LTPS Thin-Film Schottky Diode on Glass Substrate for Hydrogen Sensing Applications

A $hbox{Pd/TiO}_{2}$/n-type low-temperature-polysilicon (n-LTPS) MOS thin-film Schottky diode fabricated on a glass substrate for hydrogen sensing is reported. The n-LTPS is an excimer-laser-annealed and $hbox{PH}_{3}$ -gas-plasma-treated amorphous-silicon (a-Si) thin film. At room temperature and $-$2-V bias, the developed MOS Schottky diode exhibited a high signal ratio of 1540 to 50 ppm of hydrogen gas, with a fast response time of 40 s, respectively. The signal ratio is better or comparable with that of other reported MOS-type hydrogen gas sensors prepared on Si or III–V compound substrate. In addition, the signal ratio is 7.6, 14, and 30 times over other interfering gases of $ hbox{C}_{2}hbox{H}_{5}hbox{OH}$, $hbox{C}_{2}hbox{H}_{4}$ , and $hbox{NH}_{3}$ at room temperature and a concentration of 8000 ppm at $-$2-V bias, respectively. Thus, the developed MOS Schottky diode shows promise for the future development and commercialization of a low-cost hydrogen sensor.      

Eigendecomposition of Images Correlated on $S^{1}$, $S^{2}$, and $SO(3)$ Using Spectral Theory

Eigendecomposition represents one computationally efficient approach for dealing with object detection and pose estimation, as well as other vision-based problems, and has been applied to sets of correlated images for this purpose. The major drawback in using eigendecomposition is the off line computational expense incurred by computing the desired subspace. This off line expense increases drastically as the number of correlated images becomes large (which is the case when doing fully general 3-D pose estimation). Previous work has shown that for data correlated on S ¹ , Fourier analysis can help reduce the computational burden of this off line expense. This paper presents a method for extending this technique to data correlated on S ² as well as SO(3) by sampling the sphere appropriately. An algorithm is then developed for reducing the off line computational burden associated with computing the eigenspace by exploiting the spectral information of this spherical data set using spherical harmonics and Wigner-D functions. Experimental results are presented to compare the proposed algorithm to the true eigendecomposition, as well as assess the computational savings.