Effects of width scaling and layout variation on dual damascene copper interconnect electromigration

Electromigration versus line width in the 0.12–10 μm range and the configuration of the via/line contact in dual damascene Cu has been investigated. There are two scenarios for width scaling impact on electromigration. One is the width < 1 μm region, in which the MTF shows a weak width dependence, except for the via-limited condition. The other is the width > 1 μm region, in which the MTF shows a strong width dependence. A theory was proposed to explain the observed behavior. For polycrystalline lines (width > 1 μm), the dominant diffusion paths are a mixture of grain boundary and surface diffusion. The activation energy for the dominant grain boundary transport (width > 1 μm) is approximately 0.2 eV higher than that of the dominant surface transport (width  1 μm). The derived activation energies for grain-boundary and surface diffusion are obtained from Cu drift velocity under electromigration stressing. The mechanisms governing the electromigration lifetime of interconnects leads to via interconnect design rules for maximizing lifetime being identified.     

多层金属化系统中的蓄水池效应

对于W通孔多层金属化系统来说,金属离子蓄水池效应对其电迁移寿命的影响很大.设计了12种不同的蓄水池结构,并进行电迁移实验;考察了蓄水池面积、通孔位置、数目及大小等对互连线的电迁移寿命的影响,得出蓄水池的面积是影响电迁移寿命的主要因素.     

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low-k materials (k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.     

Analysis of the reservoir effect on electromigration reliability

The reservoir effect on electromigration reliability is analyzed using the normalized vacancy concentration distribution in the reservoir region of multi-level Al–0.5%Cu interconnect structure. With the assumption of steady state for the vacancy concentration and the fact that no current flow conducts in the reservoir region during electromigration test, a simple equation for calculation of the vacancy concentration is induced. Then direct calculation of the equation is carried out utilizing the hydrostatic stress distribution computed from finite element method to estimate the probability of initial void formation in the reservoir region. Finally, three multi-level Al–0.5%Cu interconnect structures with different reservoir lengths are constructed and electromigration lifetime for the structures is measured to clarify these computational results. From the results of this study, we conclude that the normalized vacancy concentration under the assumption of steady state can be regarded as a quantitative parameter to analyze the reservoir effect on electromigration reliability.     

Width dependence of the effectiveness of reservoir length in improving electromigration for Cu/Low-k interconnects

Reservoir effect of electromigration (EM) reliability has been investigated in Cu/low-k dual-damascene interconnects with varied reservoir lengths. However, the effectiveness of the reservoir effect in improving EM reliability as a function of line width has not been studied till now. In this work, experimental studies of the reservoir effect for both narrow and wide metal lines are conducted. It is found that the reservoir effect is more effective for a narrow line. The variation of the reservoir effectiveness as a function of the reservoir length is found to be different for different line width, and atomic flux divergence (AFD) distribution in the interconnect is used to explain the experimental results with good agreement.     

Effect of current reversal on the failure mechanism of Al-Cu-Si narrow interconnects

The work reported here concerns the effect of a brief exposure to a reversed current on the electromigration failure of narrow Al-Cu thin-film conducting lines. While the precise mechanism by which Cu retards electromigration in AlCu alloys is not fully understood, the consistent observation that electromigration failure is preceded by the sweeping of Cu from the failure site can be used to improve electromigration resistance by stabilizing the distribution of Cu. One way of doing this is to expose the Al-Cu line to a reverse current for some period of time. The present work shows that this method is particularly effective in thin lines with “quasi-bamboo” microstructures. It has the effect of building a reservoir of Cu at the upstream ends of the polygranular segments that are the preferred failure sites, and significantly increases both the mean time to failure, and the time to first failure of a distribution of lines. It can be inferred from these results that Al-Cu lines that conduct alternating current should be exceptionally resistant to electromigration failure.     

互连铝通孔电迁移特征及其可靠性研究

研究了超大规模集成电路铝互连系统中铝通孔的电迁移失效机理及其可靠性寿命评价技术.试验采用CMOS和BiCMOS两种工艺各3组的铝通孔样品,分别在三个温度、恒定电流的加速条件下试验,以通孔开路为电迁移失效判据,最后得到了在加速条件下互连铝通孔的电迁移寿命,其结果符合标准的威布尔分布,试验准确可行.通过电迁移模型对试验数据进行了拟合,得到了激活能、电流加速因子和温度加速因子,计算出了正常工作条件下通孔电迁移的寿命,完成了对铝通孔电迁移的研究和寿命评价.     

Relationship between texture and electromigration lifetime in sputtered AI-1% Si thin films

The relationship among the grain structure, texture, and electromigration lifetime of four Al-1% silicon metallizations produced under similar sputtering conditions was explored. The grain sizes and distributions were similar and the grain structure was near-bamboo for all metallizations. All metallizations exhibited a near-(111) fiber texture, as determined by the pole figure technique. Differences in electromigration behavior were noted. Three of the metallizations exhibited a bimodal failure distribution while the fourth was monomodal and had the longest electromigration lifetime. The electromigration lifetime was directly related to the strength of the (111) fiber texture in the metallization as anticipated. However, whereas the grain size distribution has an effect on the electromigration lifetime when metallization lines are several grains wide, the electromigration lifetime of these near-bamboo metallizations appeared independent of the grain structure. It was also observed that a number of failures occurred in the 8 μm interconnect supplying the 5 μm wide test lines. This apparently reflects an increased susceptibility of the wider interconnect lines to electromigration damage.     

Investigation of the influence of thermal treatment on interconnect-barrier interfaces in copper metallization systems

In this paper, we present recent results dealing with the influence of a high temperature anneal on the Cu–Ta interface in copper metallization systems. The electromigration lifetime data show a strong dependency of the electromigration robustness on the temperature budget. A bimodal behavior was observed after annealing the metallization at temperatures of 470 °C and above for more than 10 h. Surprisingly the high temperature anneal produces a late failure mode in electromigration lifetime tests resulting in a 10 times higher MTTF. To understand the influence of temperature pretreatment on electromigration behavior, TEM and SIMS have been performed on untreated samples (as fabricated) and on samples stored at 500 °C for 10 h. The TEM investigation shows no significant change in Cu grain size due to the high temperature. The Tof-SIMS investigations show that Ta diffuses into the Cu interconnect at the high temperature. A diffusion length for Ta of about 150 nm was observed for samples stored at 500 °C for 10 h. This effect has a strong impact on the results of the electromigration tests, done on lines after high temperature anneal.     

The isocurrent test: A promising tool for wafer-level evaluation of the interconnect reliability

A highly accelerated wafer-level electromigration test, the isocurrent test, is presented. A constant high current is used to give both the current and temperature stress to a 4-point resistor with a bonding pad layout which minimizes temperature gradients. The test is used to evaluate unpassivated Al---Cu and passivated Al---Si---Cu lines of different line width. Log normal failure distributions are obtained and the line width dependence of the MTTF and DTTF is similar to that observed in classical electromigration tests. A storage test at 250 °C clearly deteriorates the lifetime of 0.5 and 0.7 μm passivated lines. This is probably due to stress induced void formation.     

Electromigration behavior of dual-damascene Cu interconnects––Structure, width, and length dependences

Experiments were performed to study the effect of line width and length, and the results revealed interesting differences in electromigration behavior of via-fed upper and lower layer dual-damascene test structures. The observed location of electromigration induced void in upper and lower layer test structures cannot be completely explained by the theory of current gradient induced vacancy diffusion. The electromigration median time to failure (MTF) were found to be dependent upon the line width for the lower layer test structures while it remained unaffected in the case of upper layer test structure. Cu/dielectric cap interface acting as the dominant electromigration path and the current crowding location being near the Cu/dielectric cap interface for lower layer structures due to structural differences, explain this behavior. Similarly, short length upper and lower layer test structures exhibited completely different characteristics. The back stress effect on short lines was evident on both upper and lower layer structures, however, only the upper layer showed two distinct via and line failure mechanisms. These observed effects are specific to Cu dual-damascene structures and can have major technological implications for electromigration reliability assessment.     

Electromigration of Cu/low dielectric constant interconnects

Electromigration in damascene Cu/low dielectric constant interconnects with overlayers of CoWP, Ta/TaN, SiN_x or SiC_xN_yH_z and Cu(Ti) interconnects capped with SiN_x was studied. The results showed that the migration fast path in the bamboo-like lines primarily occurred at the interface. Cu lines fabricated with various forms of TaN/Ta liner including PVD TaN, ALD TaN, and PVD body centered cubic α- or tetragonal β-Ta liners were also investigated. Both thin surface layers of CoWP or Ta/TaN and the addition of Ti in the Cu lines significantly reduced the Cu/cap interface diffusivity and remarkably improved the electromigration lifetime when compared with Cu lines capped with SiN_x or SiC_xN_yH_z. Activation energies for electromigration were found to be 1.9–2.4 eV, 1.4 eV, 0.85–1.1 eV, and 1.3 eV for the bamboo-like Cu lines capped with CoWP, Ta/TaN, and SiN_x or SiC_xN_yH_z, and Cu(Ti) bamboo lines capped with SiN_x, respectively. The structural phase of the Ta was found to have an insignificant effect on the Cu mass flow rate. A large via size, thicker liner and/or stable connected exposed liner can provide a longer lifetime and tighter lifetime distribution, at the expense of chip density or effective Cu line conductivity.     

A highly reliable low temperature Al-Cu line/via metallization forsub-half micrometer CMOS

In this paper we present significant advances over the current art in terms of enhanced electromigration lifetime, low temperature deposition, and improved damascene capability of Al-Cu via/line structure. The electromigration data shows that Al-Cu via/interconnect structure deposited by a new low pressure sputtering process (LPS) results in at least “9×” better electromigration lifetime (t₅₀) to that of conventionally used CVD W stud/Al-Cu interconnect structure. This significant improvement in the reliability may be attributed to the “breakthrough” in void-free filling of high aspect ratio (3 to 4) sub-half micrometer vias with low resistivity metal such as Al-Cu at as low temperature as room temperature. The LPS process eliminates the need of a collimator normally used to fill or coat the vias and improves throughput by a factor of 5× at least compared to collimation. The extendibility of this technique beyond 0.25 μm contact geometries is demonstrated. The integration of the LPS process, Al-Cu via/interconnects using damascene process demonstrates a working 512 K SRAM chip with 0.5 μm minimum groundrules     

Study of the impact of electromigration on integrated circuit performance and reliability at design level

Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, as it is responsible for the performance degradation. High values of temperature and current density accelerate the damage, causing an increase in the lines resistance and circuit lifetime reduction. In this work, a method is proposed to evaluate the electromigration effects in an operational amplifier circuit performance due the void growth induced by electromigration. The performance parameters are simulated by AC, DC and transient analysis for a specific temperature and time interval and the results are compared with a circuit free of electromigration. The method is used to investigate the circuit response regarding the unit gain frequency, voltage gain, cutoff frequency, output swing voltage and settling time. There are three lines that can be traditionally classified as critical due to the large current density they carry. Nevertheless, a fourth line, which has a current density below the maximum limit set by the technology being typically considered as non-critical from the layout design point of view, leads to significant reduction of the voltage gain and voltage swing, of about 59% and 14% in 5 years.     

Experimental characterization and modelling of electromigration lifetime under unipolar pulsed current stress

The electromigration behaviour of Cu/SiCOH interconnects carrying unipolar pulsed current with long periods (i.e. 2, 16, 32 and 48 h) is presented in this study. Experimental observations suggest that the electromigration behaviour during void growth can be described by the ON-time model and that the lifetime of the Cu/SiCOH interconnects is inversely related to the duty cycle. Numerical simulation is carried out to compute the time required to nucleate a void under unipolar pulsed current stress conditions. The time to void nucleation is found to vary proportionally to the inverse square of the duty cycle and is independent of frequency at 1 Hz and higher. By computing the stress evolution in interconnects with short length, it was shown that the product of the unipolar pulsed current’s duty cycle and current density, i.e. average current density, is equivalent to the current density of a constant current (D.C.) stress. The simulation results suggest (d · jL)_crit as the equivalent critical current density-length product under unipolar pulsed current condition. Both the experimental and simulation results show that duty cycle has an effect on the electromigration lifetime of interconnects carrying unipolar pulsed current.     

Electromigration reliability of tungsten and aluminum vias andimprovements under AC current stress

The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region (<200 Hz) and four times the DC lifetime in the normal frequency region (> 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model     

W-plug via electromigration in CMOS process

We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process. Failure occurs at the top or bottom of a W-plug via. We design a series of via chains, whose size ranges from 0.35 to 0.55 μm. The structure for the via electromigration test is a long via chain, and the layer in the via is Ti/TiN/W/TiN. Using a self-heated resistor to raise the temperature of the via chain allows the structure to be stressed at lower current densities, which does not cause significant joule heating in the plugs. This reduces the interaction between the plug and the plug contact resistance and the time-to-failure for the via chain. The lifetime of a W-plug via electromigration is on the order of 3 × 107 s, i.e., far below the lifetime of metal electromigration. The study on W-plug via electromigraion in this paper is beneficial for wafer level reliability monitoring of the ultra-deep submicron CMOS multilayer metal interconnect process.     

Improved understanding of metal ion reservoirs within barrier-metal systems

Within integrated circuits there are many instances where low current density lines feed directly (without a via) into a single line of much higher current density, for example with clock or power supply distribution. This work demonstrates and discusses increased lifetime with increasing numbers of current feed lines in a barrier metal interconnect system. The low current density feed lines (branches) act as reservoirs or sources of additional Al and Cu ions, which can re-fill portions of voids and/or slow void growth in the high current density line (trunk). It is discussed that any area of metal at a lower current density might be considered a reservoir or source of metal ions for higher current density regions, and can effectively extend the lifetime of the higher current density region. Narrow lines may get more benefit than wide lines. Increasing reservoir size will increase lifetime, within limits.     

Electromigration characteristics of tungsten plug vias under pulseand bidirectional current stressing

Using Kelvin test structures, electromigration performances of selective CVD tungsten filled vias under DC, pulsed DC, and AC current signals have been studied. The metallization consists of Al-Cu/TiW multilevel metals. The via electromigration lifetime exhibits a current polarity dependence. The via AC lifetimes are found to be much longer (more than 1000×) than DC lifetimes under the same peak stressing current density. The via lifetimes under pulsed DC stress of 50% duty factor are twice the DC lifetimes at low-frequency regions (<200 Hz) and 4-5 times the DC lifetimes at high-frequency regions (>10 kHz). The results are in agreement with the vacancy relation model     

Electromigration under time-varying current stress

Interconnect failure as a result of electromigration is one of the major IC reliability concerns. The continuing trend of scaling-down feature sizes has exacerbated this problem. Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed DC (local V_CC and V_SS lines) and bidirectional AC (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. The goal of this review is to clarify the failure mechanisms by examining different metallization systems (Al–Si, Al–Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under pulsed DC and AC stress in a wide frequency range (from millihertz to 500 MHz). Based on these experimental results, a defect relaxation model under pulsed DC stress and a damage healing model under AC stress are developed, and electromigration design rules under these circumstances are proposed. This review shows that in the circuit operating frequency range, the “design rule current” is the time-average current for both pulsed DC and AC cases. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.