Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

This paper describes an architecture for stable high-order /spl Sigma//spl Delta/ modulation. The architecture is based on a hybrid /spl Sigma//spl Delta/ modulator, wherein hybrid integrators replace conventional analog integrators. The hybrid integrator, which is a combination of an analog integrator and a digital integrator, offers an increased dynamic range and helps make the resulting high-order /spl Sigma//spl Delta/ modulator stable. However, the hybrid /spl Sigma//spl Delta/ modulator relies on precise matching of analog and digital paths. In this paper, a calibration technique to alleviate possible mismatch between analog and digital paths is proposed. The calibration adaptively adjusts the digital integrators so that their transfer functions match the transfer functions of corresponding analog integrators. Through behavioral-level simulations of fourth-order /spl Sigma//spl Delta/ modulators, the calibration technique is verified.     

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The derivation of the time-interleaved continuous-time /spl Delta//spl Sigma/ modulator from a discrete-time /spl Delta//spl Sigma/ modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass /spl Delta//spl Sigma/ modulator is designed in a 0.18-/spl mu/m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively.     

A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers

A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and /spl Sigma//spl Delta/ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order /spl Sigma//spl Delta/ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass /spl Sigma//spl Delta/ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW.     

Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme

Since the 1970's, the analog switches in switched-capacitor (SC) circuits are operated by nonoverlapping bi-phase control signals (/spl phi//sub 1/, /spl phi//sub 2/). The nonoverlapping of these two phases is essential for successful SC operation since, a capacitor inside an SC circuit can discharge if two switches, driven by /spl phi//sub 1/ and /spl phi//sub 2/, are turned on simultaneously. Moreover, since 1983, two additional phases are generally used in many SC circuits, which consist of advanced versions of /spl phi//sub 1/ and /spl phi//sub 2/. These two additional phases overcome the problem of signal-dependent charge injection. This paper presents a low-power and low-voltage analog-to-digital (A/D) interface module for biomedical applications. This module provides an A/D conversion based on a mixed clock-boosting/switched-opamp (CB/SO) second-order sigma-delta (/spl Sigma//spl Delta/) modulator, capable of interfacing with several different types electrical signals existing in the human body, only by re-programming the output digital filter. The proposed /spl Sigma//spl Delta/ architecture employs a novel single-phase scheme technique, which improves the dynamic performance and highly reduces the clocking circuitry complexity, substrate noise and area. Simulated results demonstrate that the signal integrity can be preserved by exploring the gap between the high conductance region of pMOS and nMOS switches at low power-supply voltages and the fast clock transitions that exist in advanced CMOS technologies. The mixed CB/SO architecture together with the overall distortion reduction resulting from using the proposed single-phase scheme, result that the dynamic range of the modulator is pushed closer to the theoretical limit of an ideal second-order /spl Sigma//spl Delta/ modulator.     

A comparative analysis of parallel delta-sigma ADC architectures

Parallelism can be used to increase the conversion bandwidth of delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADCs). Time-interleaved, parallel /spl Delta//spl Sigma/, and frequency-band-decomposition ADCs are three parallel architectures that are shown to be explained using the same underlying theory. This common structure is then used to explore the design tradeoffs among these architectures. It is shown that the frequency-band-decomposition ADC is insensitive to channel mismatches but it is the most complex to design. The Hadamard modulated parallel /spl Delta//spl Sigma/ ADC provides the best performance (without considering nonidealities) but requires large digital filters. Finally, a randomization technique is described that can be used with parallel /spl Delta//spl Sigma/ architectures to spread out the tonal energy due to channel mismatches over the frequency spectrum.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling /spl Delta//spl Sigma/ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the /spl Delta//spl Sigma/ modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the /spl Delta//spl Sigma/ modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order /spl Delta//spl Sigma/ modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a 0.25-/spl mu/m standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.     

A noise-shaped switching power supply using a delta-sigma modulator

A technique to reduce in-band tones in switch-mode power supplies is described. It takes advantage of the noise-shaping properties of the delta-sigma (/spl Delta//spl Sigma/) modulator to eliminate the spikes normally present in switching power supplies. A framework is introduced for comparing the conventional pulsewidth modulated (PWM) controller and this approach. A buck converter test circuit is constructed that is designed for a PWM controller clocked at 200 kHz and then substituted with a /spl Delta//spl Sigma/ modulator controller clocked at 400 kHz. The RMS noise power of the PWM controller is 14.9 mW compared to the rms noise power for the /spl Delta//spl Sigma/ modulator of 75.85 mW measured in a 2-MHz bandwidth. Although the /spl Delta//spl Sigma/ modulator rms noise power is higher, the noise floor is below the tones seen at the output of the PWM controller. A multibit /spl Delta//spl Sigma/ modulator controller, however, provides a significant reduction in the spectral output of the power supply. Values of 3.75 and 0.24 mW rms noise power are observed at the output of a 2-bit and 4-bit /spl Delta//spl Sigma/ modulator controller, respectively.     

A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.     

A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture

In this paper, we present a new continuous-time bandpass delta-sigma (/spl Delta//spl Sigma/) modulator architecture with mixer inside the feedback loop. The proposed bandpass /spl Delta//spl Sigma/ modulator is insensitive to time-delay jitter in the digital-to-analog conversion feedback pulse, unlike conventional continuous-time bandpass /spl Delta//spl Sigma/ modulators. The sampling frequency of the proposed /spl Delta//spl Sigma/ modulator can be less than the center frequency of the input narrow-band signal.     

Breaking the feedback loop of a class of /spl Sigma//spl Delta/ A/D converters

/spl Sigma//spl Delta/ modulation is the currently successful technique used to perform high resolution analog-to-digital conversion. In spite of its practical success, its theoretical signal analysis has remained limited because a /spl Sigma//spl Delta/ modulator contains of a feedback loop that includes a nonlinear operation, i.e., the amplitude discretization or quantization. The feedback allows us to use oversampling to compensate for the limitations of the quantizer in resolution and in precision, which are typical of analog circuits. However, because of the lack of signal analysis, it is still not clear how much resolution of conversion can be gained as a function of the oversampling. We show that for a large class of /spl Sigma//spl Delta/ modulators, the feedback loop theoretically yields an equivalent feedforward signal flow graph, at least for constant inputs. This is possible thanks to remarkable modulo properties of these modulators. This equivalence can be asymptotically extrapolated to time-varying inputs with increasing oversampling. Although the exact components of the equivalent graph are not currently known in general, the theoretical structure of the feedforward graph is sufficient to point out misconceptions in the current knowledge on the final resolution of an nth-order /spl Sigma//spl Delta/ modulator. Specifically, except when the modulator is "ideal", the global resolution of conversion increases by n bits per octave of oversampling, instead of the currently believed rate of n+(1/2) bits/octave.     

Continuous-time /spl Delta//spl Sigma/ modulators using distributed resonators

We derive a method for using distributed resonators in /spl Delta//spl Sigma/ modulators and demonstrate these /spl Delta//spl Sigma/ modulators have several advantages over existing /spl Delta//spl Sigma/ modulator architectures. Like continuous-time (CT) /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators do not require a high-precision track-and-hold, and additionally can take advantage of the high-Q of distributed resonators. Like discrete-time /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators are relatively insensitive to feedback loop delays and can subsample. We present simulations of several types of these /spl Delta//spl Sigma/ modulators and examine the challenges in their design.     

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.     

Cascade /spl Sigma//spl Delta/ modulator with digital correction for finite amplifier gain effects

A simple and fully digital solution to correct the effect of amplifier finite gain in cascade /spl Sigma//spl Delta/ modulators is presented. The main contribution of this study is a simple digital method to evaluate the integrator pole errors, which are further taken into account to modify the reconstruction filter. The method is applied to a 2-1 cascade modulator.     

A fast block-based nonlinear decoding algorithm for /spl Sigma//spl Delta/ modulators

Previous work has established that the digital output of a /spl Sigma//spl Delta/ modulator as an A/D converter contains more information about the analog input than is extracted with conventional linear filtering. Under reasonable mathematical assumptions, optimal nonlinear decoding of the digital output can achieve significantly larger signal-to-noise ratios than linear filtering. However, the hitherto proposed decoding algorithms only demonstrate conceptual feasibility and are impractical from a computational point of view. We present a new block-based decoding algorithm that, like previous work, employs projections onto convex sets. The algorithm owes its speed to a change of projection norm, an accelerated convergence scheme, and a decimation-like subsampling; it is on the order of 10/sup 4/-10/sup 5/ times faster than one previously published algorithm for typical parameter values, and about 2-10 times slower than linear decoding. The new algorithm is applicable to all currently popular /spl Sigma//spl Delta/ architectures.<>     

Driven interval shift dynamics in sigma-delta modulators and phase-locked loops

In this paper, we show how consideration of the first-order sigma-delta (/spl Sigma//spl Delta/) modulator with sampled periodic input motivates study of the maps known mathematically as driven interval shifts. We derive new results concerning the behavior of these maps, and apply these results to provide new insight into the behavior of /spl Sigma//spl Delta/ modulators and phase-locked loops. We will see that viewing these systems through the mechanism of the driven interval shift allows us to identify common features in their behavior.     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays

An analytical design methodology for continuous-time (CT) bandpass (BP) /spl Sigma//spl Delta/ modulators is presented. Second- and fourth-order tunable continuous time BP /spl Sigma//spl Delta/ modulator design equations are presented. A novel /spl Sigma//spl Delta/ loop architecture, where the traditional CT BP loop filter function is replaced with the filter function with fractional delays, is proposed. Validity of the methodology is confirmed by mixed-signal behavioral simulations.     

Reconfigurable ADCs enable smart radios for 4G wireless connectivity

A reconfigurable ADC based on a 2-2 modified cascaded /spl Sigma//spl Delta/ modulator designed for a GSM/WCDMA/WLAN/WiMAX zero-IF receiver has been presented. Employing the second-order feedforward /spl Sigma//spl Delta/ modulator in a 2-2 modified cascaded configuration, a high linearity over 100 kHz/2 MHz/10 MHz signal bandwidth is achieved. The P-DWA technique is applied in the first feedback 4-b DAC to eliminate the spurious tones associated with the multibit DAC nonlinearity in the WLAN/WiMAX modes.