Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

This paper reports the analyses of three techniques for phase noise reduction in the complementary metal‐oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28‐nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1‐MHz frequency offset for an oscillation frequency of 10 GHz. © 2015 The Authors International Journal of Circuit Theory and Applications Published by John Wiley & Sons Ltd.     

Phase noise characterization of oscillators through Ito calculus

Recent phase noise analysis techniques of oscillators mainly rely on solving a stochastic differential equation governing the phase noise process. This equation has been solved in the literature using a number of mathematical tools from probability theory like deriving the Fokker–Planck equation governing the phase noise probability density function. Here, a completely different approach for solving this equation in presence of white noise sources is introduced that is based on the Ito calculus for stochastic differential equations. Time‐domain analytical expressions for the correlation of the noisy variables of the oscillator are derived that in asymptotically large times give the steady‐state stochastic correlations as well as the power spectral densities of the variables. The validity of the new approach is verified by comparing its results against extensive Monte‐Carlo simulations. This approach is applied to an oscillator with a dielectric resonator at 4.127 GHz, and a very good agreement between its results with those of the Monte‐Carlo simulations and the previous approaches is observed. Copyright © 2014 John Wiley & Sons, Ltd.     

LC‐active VCO for CMOS RF transceivers

A novel fully integrated CMOS LC tank VCO is presented. The LC tanks are implemented by exploiting the active circuit ‘boot‐strapped inductor’ (BSI), which behaves like a high‐quality factor inductor. Particularly, the LC tanks have been implemented by introducing a new version of the CMOS BSI circuit, which provides better versatility and design reliability. In order to verify the effectiveness of such an approach, a case study for 5–6 GHz direct‐conversion multi‐standard WLAN transceivers is presented. The VCO has been designed in a 0.35µm standard CMOS technology. The new BSI exhibits a high‐quality factor (higher than 25 over the all frequency range) and provides a high selectivity without introducing a relevant excess of noise, for a better spectral purity and a lower phase noise (PN) of the VCO. The overall VCO circuit consumes 9 mW. The VCO produces an oscillation in the tuning range from 4.91 to 5.93 GHz (nearly equal to 19%). The circuit exhibits a PN of ?129dBc/Hz at 1 MHz of frequency offset from the central frequency (5.4 GHz) and a FOM equal to 189.5 dBc/Hz at 100 kHz and 194.1 dBc/Hz at 1 MHz of frequency offset, respectively. Copyright © 2009 John Wiley & Sons, Ltd.     

A novel feed-forward compensation technique for single-stage fully-differential CMOS folded cascode rail-to-rail amplifier

This paper presents a novel active and passive mixed feed-forward compensation technique for single-stage CMOS folded-cascode rail-to-rail operational trans-conductance amplifiers (OTA). Simulations using 0.5 μm Agilent CMOS process parameters indicate a phase margin of around 82° with an unity gain bandwidth of 320 MHz (@1.17 pF capacitive load including the device parasitics). Also, the compensated OTA provided over 60 dB DC-gain with rail-to-rail output voltage swing as well as wide input common-mode range. This ensures optimum step response (fast and accurate settling without ringing) for the feedback amplifier in switched-capacitor signal processing applications. An improved ``fast sensing' common-mode feedback circuit with high common-mode gain is also used for the single-stage cascode OTA.     

Analyses and techniques for phase noise reduction in CMOS Hartley oscillator topology

This paper reports the analyses of the inductive degeneration , noise filter , and optimum current density techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology in a range of common conditions adopted also for a previous study on the Colpitts topology, so complementing the previous study on Colpitts topology and allowing a direct comparison between the Hartley and Colpitts topologies. The theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. Moreover, the results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter provide the demonstration of the existence of an optimum bias current density for minimum phase noise. Moreover, we will go beyond this important result, by investigating for the first time the relationship with the optimum current density for transistor minimum noise figure and other general results reported in the literature. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 10 GHz, with respect to the traditional Hartley topology. Lastly, we report a comparison under common conditions between Colpitts and Hartley topologies implementing the aforementioned techniques, which could, from a designer perspective, be useful to acquiring a few key insights about the circuit design opportunities and focus the design efforts toward specific directions for performance optimizations. Copyright © 2017 John Wiley & Sons, Ltd.     

Compact CMOS implementation of a low‐power,current‐mode programmable cellular neural network

We report on the design and characterization of a full‐analog programmable current‐mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell‐core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low‐power consumption and small‐area occupation, making it suitable for the realization of large cell‐grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey‐scale and binary image processing tasks. Results from the characterization of a preliminary CNN test‐chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd.     

Phase noise analysis in CMOS differential Armstrong oscillator topology

This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano‐scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd.     

Design and implementation of switched coil LC‐VCOs in the GHz range using the self‐inductance technique

This paper presents the design and implementation of dual‐band LC‐VCOs in the GHz‐range featuring a switched coil LC‐tank. The proposed design exploits the self‐inductance technique. The design of the coil starts from simple considerations and back‐of‐the‐envelope calculations, then electromagnetic simulations are used to optimize the coil layout. The sizing of the switch and its impact on the VCO performance are addressed as well. The VCOs have been implemented in 65 nm CMOS technology. Good correlation between simulated and measured tuning range and phase noise is obtained for all designs, thus confirming the validity and robustness of the design methodology and coil models. Copyright © 2013 John Wiley & Sons, Ltd.     

Low Phase Noise LC-VCO with Multi-Stage Filtering

A low-phase-noise CMOS voltage-controlled oscillator (VCO) with zero-bias scheme and multi-stage filtering is presented. Sharing ground with fully integrated loop filter, the PMOS-only VCO achieves a zero-bias scheme, which prevents tuning line noise from disturbing VCO output common-mode voltage and hence minimizes phase noise caused by nonlinear C-V characteristic of varactors. Top-biased current source is optimized by multi-stage filtering to reduce 1/f flicker and thermal noise. Fabricated in TSMC 180 nm CMOS process, the proposed VCO exhibits a measured oscillation frequency of 0.85~1.45 GHz, with a phase noise of -121.8~-131.3 dBc/Hz @1MHz offset over the whole band. Power consumption is 3.8~6.3mW from a 1.8V supply.     

Design of a CMOS 65-nm inductor-less VCO for ISM applications in the VHF band

This paper presents a design of a CMOS cross-coupled voltage-controlled oscillator (VCO) using active inductors (AIs) for wide-band applications and can also be applied to various wireless technologies standards. The compatibility of this design to different wireless standards highlights its potential to be implemented at the core of the communication front end in the Internet of Things (IoT). The proposed AI design employs a gyrator-C topology as the basic structure to generate an inductance. The VCO uses a cross-coupled oscillator structure with a pair of varactors to sweep the frequency. Two extra capacitors, between the AIs and the outputs of the VCO core tank, are employed to enhance the performance of the phase noise and make the VCO work similarly to a linear transconductance (LiT) oscillator. Both the AIs and the VCO are designed in the TSMC 65-nm CMOS technology, and the performance is analyzed using postsimulation results, as well as through measurements. The fundamental frequency spans from 140 to 463 MHz. Thus, the relative tuning range of this design is approximately 107%. The optimal phase noise of the design is around −97 dBc/Hz at 1-MHz offset. Furthermore, it achieves an excellent figure of merit (FOM) around −163 dBc/Hz with a direct current (DC) power consumption less than 3 mW. The proposed design shows an advantage in phase noise and power consumption in comparison with previous active inductor VCO and ring VCO designs, respectively. The final layout occupies only 0.4 × 0.62 mm² including the pads. The proposed AI-VCO shows a compact size, linear tuning, low power consumption, and good phase noise performance.     

数字中频感应加热电源的研究

针对传统模拟中频控制系统的不足,对新型数字中频控制系统进行了研究和设计。提出一种基于DSP DS80C320微控制器为控制核心,主开关元件采用IGBT的数字感应加热系统,设计了系统的主电路、控制电路的结构。针对串联型感应加热电源频率跟踪的要求,阐述了一种新型的数字锁相环(DPLL)控制方法,并对相位补偿与启动问题进行了探讨,最终给出了实验电路和实验结果。实际应用证明具有功率调节范围宽、频率变化小的优点,适用于在中频感应加热中的应用。     

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

Voltage-controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four-stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual-delay loop technique for high operation frequency. Also, a low-V_T NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65-nm TSMC CMOS technology in Cadence software under 1.2-V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm² . This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

Design of 3.1 to 10.6 GHz ultra‐wideband flat gain LNA

In this paper, a new ultra‐wideband low‐noise amplifier (LNA) is proposed. The proposed LNA has flat gain and low noise figure (NF) in the frequency range of 3.1 to 10.6 GHz. To obtain higher gain, cascode architecture is used. In this design, to have a lower NF, the noise cancellation technique applies to the cascode architecture. In addition, to have better matching at the input and output, active feedback and matching transistors are used, which also leads to better NF. To have flat gain, RLC load is used. In the proposed LNA, only one inductor is used, which leads to the smaller chip area. The proposed circuit is designed in 90 nm CMOS technology. The simulation shows NF of between 1.62 and 2.1 dB, flat gain between 11.9 and 12 dB and power consumption of 11.72 mW in the frequency range of 3.1 to 10.6 GHz. The simulation results support the theoretical predictions. Copyright © 2017 John Wiley & Sons, Ltd.     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMOS technology, a 1.78‐mW divider‐by‐two is designed with free‐running frequency of 27.92 GHz, locking‐range of 51 to 59.6 GHz, and figure‐of‐merit of 4.83 (GHz/mW). EM simulation results of the proposed and conventional structure are compared, which illustrates 56% improvement in locking‐range.     

A symmetric lattice-based wideband wide phase range digital phase shifter topology

In this paper, a novel digital phase shifter topology that achieves wideband and wide phase range is proposed. Wide frequency band operation is accomplished employing symmetrical all-pass lattice structures. Compact phase shifter size is obtained utilizing the miniaturized microwave monolithic integrated circuit (MMIC) design implementation technology. Therefore, resulting phase shifter units are suitable for various communication systems such as radar and cellular communication smart antenna arrays. This paper provides complete design equations together with design algorithm for the selected phase shift and the center frequency. Design algorithm is developed on MatLab environment. The proposed phase shifting circuit is implemented employing the commercially available 0.18-μm silicon CMOS technology. The new phase shifter topology provides 0⁰ to 360⁰ phase shift range over X-band, even beyond.     

A low-power voltage differencing buffered amplifier

A low-voltage, high-performance voltage differencing buffered amplifier (VDBA) designed using differential flipped voltage followers (DFVF) is presented in this paper. The proposed VDBA is capable of providing high transconductance and wide bandwidth (BW) with low biasing currents and buffer transfer ratio close to unity. Mathematical formulations for transconductance and buffer transfer ratio are deduced through low-frequency small signal analysis. Pre and post layout simulations for characterization of the proposed structure are carried out on Cadence Virtuoso using gpdk 0.18-μm CMOS process parameters. The transconductance of the proposed VDBA is observed to be varying from 411.8 μS to 1.374 mS for a corresponding bias current range of 10 to 75 μA, and the 3-dB bandwidth (BW) is recorded to be 1.2 GHz. The PVT analysis is carried out to show the effect of process corners. To check the robustness of the proposed VDBA, Monte Carlo analysis is performed, and results have been included in the form of histograms.     

Tunable selective receiver front end with impedance transformation filtering

A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is presented in this paper. To achieve blocker rejection comparable with surface acoustic wave (SAW) filters, we use a two‐stage architecture based on a low‐noise transconductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate ‘back folding’ by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept, a chip design of a tunable RF front end using 65 nm complementary metal‐oxide‐semiconductor (CMOS) technology is presented. In measurements, the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2–5.2 dB, out of band IIP3 > +17 dBm, and blocker P_1dB > +5 dBm over frequency range of 0.5–3 GHz. Copyright © 2015 John Wiley & Sons, Ltd.