A Flexible, Ultra-Low-Energy 35 pJ/Pulse Digital Back-End for a QAC IR-UWB Receiver

A low-energy, flexible digital back-end for the quadrature analog correlating (QAC) IR-UWB receiver, implemented in 0.13 m CMOS technology, is presented. The built-in flexibility allows the receiver to operate over a wide range of frequency bands, pulse rates, code lengths, acquisition modes, etc. This ability to dynamically trade power consumption, system performance and system reliability is crucial for application in sensor networks where energy is scarce. To avoid the large power penalty, that often accompanies the introduction of flexibility, the chip's architecture is based on nested FLEXmodules. These are small configurable modules with a local controller, that can be slowed down and clock gated individually. Communicating at 40 Mpulses/s, the resulting digital back-end consumes as little as 3.5 mW in acquisition mode and 1.5 mW during data reception. This is equivalent to an energy consumption of 35 pJ per received pulse.     

A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA

A 2-GHz single-chip direct conversion receiver achieves a 3.0-dB double-sideband noise figure, -14-dBm IIP3 and +17-dBm IIP2 with 60-mW power consumption from a 2.7-V supply. The receiver is targeted for the third generation UTRA/FDD WCDMA system. The low power consumption has been achieved with a proper partitioning and by avoiding buffering between blocks. In the differential RF front end, current boosted quadrature mixers follow the variable-gain low-noise amplifier. At the baseband, on-chip ac-coupled highpass filters are utilized to implement amplification with variable gain having small transients related to gain steps. The outputs of the analog channel selection filters are sampled directly by the two single-amplifier 6-bit pipeline A/D converters. The spurious tones due to the feedthrough of clock harmonics to the RF input increase the noise figure less than 0.1 dB. The receiver has been fabricated with a 0.35-μm 45-GHz f_T SiGe BiCMOS process     

Intermittent Operation Control Scheme for Reducing Power Consumption of UWB-IR Receiver

A low power ultra-wideband impulse radio (UWB-IR) receiver was developed in 0.18-mum CMOS. All circuits of the receiver AFE operate intermittently with a sampling clock of an analog-digital converter (ADC). The sampling rate of the ADC is equal to the pulse repetition frequency of the received signals. Power consumption of the receiver AFE is reduced by 60% using a developed intermittent operation scheme without degrading of receiver sensitivity. As a result, the power consumption of the receiver AFE is 38 mW. The receiver has a data rate of 258 kb/s over a distance of 52 m and of 10.7 Mb/s over a distance of 14 m.     

A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging

This paper presents a fully integrated flexible ultra-low power UWB impulse radio receiver, capable of cm-accurate ranging. Ultra-low-power consumption is achieved by employing the quadrature analog correlating receiver architecture, by exploiting the duty-cycled nature of the system, by operating in the sub-1 GHz band as well as by careful circuit design. Two pulse rates, 39.0625 Mpulses per second (Mpps) and 19.531 Mpps, and a wide range of processing gains (0-18 dB) are supported. Also, the acquisition algorithm and accuracy can be adapted at run time. This flexible implementation allows to dynamically trade power consumption for performance depending on the operating conditions and the application requirements. The receiver prototype was manufactured in 130 nm CMOS and the active circuit area measures 4.52 mm². The IC contains a complete analog front-end, digital backend and implements the algorithms necessary for acquisition, synchronization, data reception and ranging. Consuming 4.2 mW when operating at 39.0625 Mpps, it achieves an energy efficiency of 108 pJ/pulse. A 1.3 Mb/s wireless link over more than 10 m in an office-like environment has been demonstrated under direct line-of-sight (LOS) conditions with a raw packet-error-rate (PER) less than 10% and cm-accurate ranging.     

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

This paper presents an integrated ultra-low power analog front-end (AFE) architecture for UWB impulse radio receivers . The receiver is targeted towards applications like wireless sensor networks typically requiring ultra energy-efficient, low data-rate communication over a relative short range. The proposed receiver implements pulse correlation in the analog domain to severely relax the power consumption of the ADCs and digital backend. Furthermore a fully integrated prototype of the analog front-end, containing a PLL, programmable clocking generator, analog pulse correlator, a linear-in-dB variable gain amplifier and a 4-bit ADC, is demonstrated. Several design decisions and techniques, like correlation with a windowed LO instead of with a matched template, exploiting the duty-cycled nature of the system, operation in the sub-1 GHz band as well as careful circuit design are employed to reach ultra-low power consumption. The analog front-end was manufactured in 130 nm CMOS and the active circuit area measures 1000 $muhbox{m} times ,$1500 $muhbox{m}$. A maximum channel conversion gain of 50 dB can be achieved. Two symbol rates, 39.0625 Mpulses per second (Mpps) and 19.531 Mpps are supported. The AFE consumes 2.3 mA from a 1.2 V power supply when operating at 39.0625 Mpps. This corresponds to an energy consumption of 70 pJ/pulse. A wireless link over more than 10 $~$m in an office-like environment has been demonstrated at 19.531$~$ Mpps with a $hbox{PER} ≪ 1{rm E}-3$ under direct LOS conditions.      

基于法布里-珀罗激光器的超高重复频率光脉冲生成技术

本文提出了一种新的基于双模自注入锁定DC电流驱动的法布里-珀罗半导体激光器(FP-LD)来生成超高重复频率,高功率光脉冲的简单方法。传统的基于注入锁定增益开关调制的FP-LD产生光脉冲方法,存在输出脉冲重复率低(通常小于10GHz)、啁啾大和低输出功率的缺点。文章提出的方案中,通过一个带直流偏置的FP-LD与两个均匀光纤布拉格光栅(FBG)相连,来实现双模自注入锁定输出。该输出信号再进入一根长的、高度非线性的光纤(HNLF)中,通过自相位调制和反常色散之间的相互作用可获得高频光脉冲。实验结果,在FP-LD相邻的两个纵模同时注入锁定时,可获得了重复频率为139.6GHz宽度为1.6ps和时间带宽积为0.34的孤子光脉冲,峰值功率为120mW。我们还观察到当改变光栅的应力,可选择相间隔的两个纵模同时注入锁定,重复频率为279.2GHz的光脉冲序列,由于该脉冲序列的四波混频增益较139.6GHz序列低,因此四波混频效应不明显。该方案结构简单,成本低廉。     

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.     

2.4-GHz receiver for sensor applications

This paper describes a receiver designed to meet the stringent power consumption requirements for sensor radio, which operates at 2.4-GHz ISM band with Bluetooth. To enable the reusability of the Bluetooth system, only slight changes are made in the radio parameters. The symbol rate is decreased and the increased modulation index removes the energy maximum from the channel center, which enables a low-complexity direct-conversion receiver solution. To meet the speed and power requirements, this receiver is fabricated in a 0.13-/spl mu/m CMOS process. The 3.4-mW direct-conversion demonstrator receiver includes a low-noise amplifier, which is merged with quadrature mixers, local oscillator buffers, and one analog baseband channel with a 1-bit limiter for analog-to-digital conversion. The receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.     

An Agile, Ultra-Wideband Pulse Radio Transceiver With Discrete-Time Wideband-IF

A pulse-based CMOS ultra-wideband transmitter and receiver have been realized using a standard digital 90 nm CMOS process. The transceiver uses digital templates stored in high-speed memories for pulse generation on the transmit side and for correlation on the receive side. This allows fast band switching for multi-band operation and interferer avoidance without the requirement for fast-settling phase-locked loops. The receiver contains a 3.1–9.5 GHz broadband front-end and discrete-time intermediate frequency correlators that achieve a pulse rate of 100 Mpulses/s and has a die area of 1 ${hbox{mm}}^{2}$ while consuming 130 mA from a 1.2 V supply. The transmitter uses interleaved, intermediate frequency digital-to-analog converters followed by partial-order hold reconstruction filters that eliminate sampling images, and a quadrature RF up-converter. 1.25 nJ is spent per transmitted pulse for a pulse-repetition rate of 100 MHz while achieving a broadband image cancellation of 42 dB.      

A frequency agile monolithic QPSK modulator with spectral filteringand 75 Ω differential line driver

This monolithic modulator combines both digital signal processing and analog techniques to realize a high bit-rate quadrature phase-shift keyed (QPSK) modulator. It includes a digital baseband pulse shaping network, analog quadrature modulator, agile carrier generator, spectral shaping, and transmit power control for interfacing to wireline transmission media. Nominal data rates are 256 kbit/s with a carrier range of 8.096-20.128 MHz in 32 kHz steps. Maximum output level is 62 dBmV into a 75 Ω load. The features of 1.2 μm mixed signal BiCMOS technology permit both signal processing and power line drivers to be collocated while achieving better than 85 dB cross-talk isolation     

Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.     

Pulsed magnet system considerations for repetitive operation ofhigh-power magnetrons

A tradeoff evaluations has been performed to specify a compact, low-loss pulsed electromagnet system for a repetition rate application of high-power magnetrons. The required magnetic field is 5 to 15 kG with 1% uniformity over the magnetron volume, and the pulse repetition rate is on the order of 5 pps. To drive the magnets, a recirculating driver scheme which transfers energy back and forth between two capacitor banks has been identified as a variable low-power-loss approach. The circuit comprises a 10-kW switching power supply, a high-voltage switch network, 400-kJ capacitor banks, and magnet coils. Several recirculating drive systems operating in the voltage range of 10 to 50 kV and output currents with a pulse duration of ≈10 ms are compared relative to their power losses, system size and weight, and their limitations at high pulse repetition rates     

A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-heldterminals

The modulator IC is a mixed analog/digital transceiver component in a chip set that is designed for the hand-held terminals of the pan-European 900-MHz Groupe Special Mobile (GSM) digital cellular radio network. The concept of the radio-frequency environment in which the circuit is used is explained, focusing on the differences in existing systems. The architecture and different functions of the modulator circuit and details of the digital and analog processing in the transmission mode are discussed. The receiving mode, which is mostly based on analog processing, is highlighted. The device generates Gaussian minimum-shift-keying (GMSK) modulation and converts the received signal to 8-b words after filtering. The modulator IC uses digital waveform generation and a quadrature signal representation. This device is implemented in a 1.5-μm CMOS technology. The power consumption is less than 35 mW from a 5-V supply     

热膨胀机制产生窄带激光声信号的方法研究

为压缩激光声信号的带宽,基于热膨胀激光致声理论提出了一种采用高重频激光脉冲串产生窄带声信号的方法(重频法),推导了最优重复频率的计算过程,并通过实验测量对重频法进行了验证。以声信号在中心频率处的功率谱密度为参考标准,将重频法与长脉冲法产生窄带声信号的性能进行了比较。理论分析与实验结果表明,激光器在最优重复频率下产生的声信号窄带特性最好;最优重复频率与激光波长、光束半径以及观测角有关;激光脉冲数大于10时,重频法的性能优于长脉冲法;脉冲数为100时,在中心频率处重频法的功率谱密度比长脉冲法高9.3dB。     

An ultra-wideband transceiver architecture for low power, low rate, wireless systems

This paper presents the system architecture, modeling, and design constraints for a baseband, integrated, CMOS, impulse ultra-wideband transceiver targeting very low power consumption on the order of 1 mW. Intended for a sensor network application, the radio supports low communication rates (/spl sim/100 kpbs) and ranging capabilities over short distances (/spl sim/10 m). Based on a "mostly digital" architecture, the analog complexity is reduced by moving the A/D convertor as close to the antenna as is reasonable. Pulses are generated from simple digital switches, overlaying the signal energy on the lower FCC UWB band (0-960 MHz). Reception is achieved using baseband gain blocks feeding a time-interleaved bank of low resolution A/D converters. A window of energy is captured in time and fed to the digital backend for processing. To save power and area, the digital backend implements only a pulse template correlation filter block overlaid with an additional spreading code. As a pulse template is used, no specific channel estimation or interference cancellation is assumed. The system performance is quantified for this case and implementation tradeoffs are explored with a strong focus on reducing power consumption. In particular, the issues of modulation choice, clock generation, gain and noise figure, ADC resolution, and digital signal processing requirements will be discussed.     

中频数字接收机的工程实现

介绍了一种数字中频接收机的工程实现办法,该数字接收机具有较大的动态范围,较高的I、Q输出精度,采用的是带通采样法进行单路中频采样,数字滤波法进行数字正交相干检波。介绍了传统模拟接收机的不足和数字接收机的优点,讨论了两种数字正交相干检波方法,研究了带通欠采样的原理;根据本课题的技术指标要求进行了设计工作,设计了中频放大电路和AGC控制电路,进行了AD采样和数字相干检波部分的设计工作。结果表明,两路信号幅度的误差≤0.5%,相位的正交误差≤0.5°,满足了设计指标要求,技术指标明显优于传统的模拟接收机。     

Noncoherent ultra-wideband systems

The need for low-complexity devices with low-power consumption motivates the application of suboptimal noncoherent ultra-wideband (UWB) receivers. This article provides an overview of the state of the art of recent research activities in this field. It introduces energy detection and autocorrelation receiver front ends with a focus on architectures that perform the initial signal processing tasks in the analog domain, such that the receiver does not need to sample the UWB received signals at Nyquist rate. Common signaling and multiple access schemes are reviewed for both front ends. An elaborate section illustrates various performance tradeoffs to highlight preferred system choices. Practical issues are discussed, including, for low-data-rate schemes, the allowed power allocation per pulse according to the regulator?s ruling and the estimated power consumption of a receiver chip. A large part is devoted to signal processing steps needed in a digital receiver. It starts with synchronization and time-of-arrival estimation schemes, introduces studies about the narrowband interference problem, and describes solutions for high-data-rate and multiple access communications. Drastic advantages concerning complexity and robustness justify the application of noncoherent UWB systems, particularly for low-data-rate systems.     

Design and analysis of an energy-efficient O-QPSK coherent IR-UWB transceiver with a 0.52° RMS phase-noise fractional synthesizer

This paper explores an energy-efficient pulsed ultra-wideband (UWB) radio-frequency (RF) front-end chip fabricated in 0.18-μm CMOS technology,including a transmitter,receiver,and fractional synthesizer.The transmitter adopts a digital offset quadrature phase-shift keying (O-QPSK) modulator and passive direct-phase multiplexing technology,which are energy-and hardware-efficient,to enhance the data rate for a given spectrum.A passive mixer and a capacitor cross-coupled (CCC) source-follower driving amplifier (DA) are also designed for the transmitter to further reduce the low power consumption.For the receiver,a power-aware low-noise amplifier (LNA) and a quadrature mixer are applied.The LNA adopts a CCC boost common-gate amplifier as the input stage,and its current is reused for the second stage to save power.The mixer uses a shared amplification stage for the following passive IQ mixer.Phase noise suppression of the phase-locked loop (PLL) is achieved by utilizing an even-harmonics-nulled series-coupled quadrature oscillator (QVCO) and an in-band noise-aware charge pump (CP) design.The transceiver achieves a measured data rate of 0.8 Gbps with power consumption of 16 mW and 31.5 mW for the transmitter and the receiver,respectively.The optimized integrated phase noise of the PLL is 0.52° at 4.025 GHz.     

A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low data rate applications

A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of ?92 dBm for a 10^?3 BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).     

Low complexity correlation receiver for rate variable SQAM modem

The performance of a low complexity correlation receiver for a rate variable SQAM modem is analytically and experimentally studied. It is found that the proposed receiver performs well for a range of SQAM signals by adjusting the amplitude parameter `B' of the receive correlation pulse. The authors demonstrate that the suggested SQAM receiver would be very well suited for use in low cost as well as bandwidth and power limited satellite broadcasting systems such as a data broadcasting USAT (ultra small aperture terminal) network