共查询到18条相似文献,搜索用时 62 毫秒
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由于受热力学基本定律的限制 ,Si集成电路技术的发展已经日益接近极限 ,而 Si Ge材料的引入使得占据小于 1GHz频段的 Si产品可以进一步覆盖 2~ 30 GHz的 RF和无线通信市场。根据前人的材料研究工作 ,在普通 Si器件性能模拟的基础上 ,进一步研究长沟应变 Si Ge器件的模拟 ,引入了插值所得的近似因子以修正 silvaco中隐含的 Si Ge能带模型和迁移率参数。然后依据修正后的模型对 Si Ge PMOS进行更为精确的二维模拟 相似文献
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SiGe技术和SOI技术将是21世纪硅集成的重要技术,它们相互补充,改善晶体管的速度 和性能。本文介绍了SiGe技术、器件和应用。 相似文献
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报道了第一支0.25um栅长n型Si/SiGe调制掺杂场效应晶体管的制作和器件特性结果,器件用于超高真空/化学汽相淀积(UHV/CVD)制作的器件,在300K(77K)下,应变Si沟道的迁移率和电子薄层载流子的深度为1500(9500)cm2/V.s和2.5×10^12(1.5*10^10)cm^-2,器件电流和跨导分别为325mA/mm和600mS/mm,这些值远优于Si MESFET,它们可与所获得的GaAs/Al-GaAs调制掺杂晶体管的结果相媲美。 相似文献
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Bongki Mheen Young-Joo Song Jin-Young Kang Kyu-Hwan Shim Songcheol Hong 《Materials Science in Semiconductor Processing》2004,7(4-6):375
As a boron diffusion barrier, a 20 nm-thick Si0.8Ge0.2 layer was successfully utilized in n-channel MOSFETs for implementing a retrograded well structure. Compared with the conventional Si CMOS process, the developed n-channel MOSFET process provides an enhanced transconductance (7%) and lower sub-threshold swing which is nearly unchanged even at an increased drain-source voltage. Especially, because sub-threshold leakage current is one of the key issues in the MOS device scaling due to reduced threshold voltage, the usage of a Si0.8Ge0.2 layer in n-channel MOSFET was verified to be useful for low power and high performance even under aggressive scaling constraints. 相似文献
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通过理论分析与计算机模拟 ,给出了以提高跨导为目标的 Si/ Si Ge PMOSFET优化设计方法 ,包括栅材料的选择、沟道层中 Ge组分及其分布曲线的确定、栅氧化层及 Si盖帽层厚度的优化和阈值电压的调节 ,基于此已研制出 Si/ Si Ge PMOSFET器件样品 .测试结果表明 ,当沟道长度为 2μm时 ,Si/ Si Ge PMOS器件的跨导为 45 m S/ mm(30 0 K)和 92 m S/ mm (77K) ,而相同结构的全硅器件跨导则为 33m S/ mm (30 0 K)和 39m S/ m m (77K) . 相似文献
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阐述了SiGe器件的主要研究方向以及国内外对SiGe材料和器件的研究情况,并对SiGe器件与Si器件和GaAs器件的发展前景进行了比较。 相似文献
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The integration of laser annealing in SiGe and Ge based MOS devices is investigated by means of numerical simulations. Our simulation code is based on two modules: the former simulates the interaction between the laser light and the transistor structure to estimate the heating, the latter simulates heat diffusion, phase changes and material redistribution under irradiation. The model is calibrated in the case of different atomic species (namely Si, Ge and common dopant impurities), considering the thermal properties of the materials and the impurity depending diffusivity in the solid, liquid and interfacial region. We present several simulation results obtained by varying materials, implanted impurity profiles and geometry of the CMOS-like structures. With the support of the simulation results we discuss the possible perspectives of the excimer laser annealing application to the fabrication of post-Si CMOS devices. In particular, we show that by using Ge and SiGe materials the process window for a melting process is larger with respect to the case of traditional Si based devices. 相似文献
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为抑制SiGeHBT基区生长过程中岛状物生成,降低位错密度,基于渐变温度控制方法和图形外延技术,结合BiCMOS工艺,研发了在Si衬底上制备高质量Si1-xGex基区的外延生长方法。通过原子力显微镜(AFM)、扫描电子显微镜(SEM)、X射线双晶衍射(XRD)测试,显示所生长的Si1,Gex基区表面粗糙度为0.45nm,穿透位错密度是0.3×103~1.2×103cm-2。,在窗口边界与基区表面未发现位错堆积与岛状物。结果表明,该方法适宜生长高质量的SiGeHBT基区,可望应用于SiGeBiCMOS工艺中HBT的制备。 相似文献
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