GaAs Schmitt trigger memory cell design

A novel GaAs five-transistor static memory cell derived from a Schmitt trigger is proposed. The memory cell overcomes MESFET subthreshold leakage loss by using a self ground-shifting technique which limits the leakage current flow to the cell. Compared with conventional GaAs SRAM cells, it offers small area and as well as fast read/write cycles. A 1 Kb prototype implemented in 1 μm nonself-aligned GaAs MESFET technology exhibited read and write access times of the order of 2.0 ns     

GaAs/AlGaAs dynamic random access memory cell

A single-transistor dynamic random access memory circuit using a GaAs/AlGaAs structure as the storage cell and modulation-doped field-effect transistors for memory accessing and output sensing has been developed. The functionality of the memory is demonstrated and a storage time of 5.4s is measured at room temperature.<>     

Block-based multiperiod dynamic memory design for low data-retention power

Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN/sup 2/) steps our algorithm computes K refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.     

High-speed GaAs static random-access memory

An 8-bit fully decoded RAM test circuit has been designed and fabricated using enhancement-mode GaAs-MESFET's with the LPFL circuit approach. Correct operation of the circuit has been observed for a supply voltage varying from 3.5 to 7 v. An access time of 0.6 ns was measured for a total power consumption of 85 mW under nominal operating conditions. This circuit was used to develop and validate both a design strategy and computer-aided design (CAD) tools oriented towards cache or buffer memories of realistic complexity. It is shown that a performance-optimized 1-kbit RAM exhibiting an access time of 1.1 ns for a power dissipation of 850 mW would be feasible with the present fabrication technology.     

GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 μm non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps     

GaAs trickle transistor dynamic logic

A GaAs dynamic logic gate is proposed which uses a trickle transistor to compensate for leakage from the precharged node. This trickle transistor dynamic logic (TTDL) circuit is configured as a domino logic gate and a differential cascode voltage switch logic (CVSL) gate. Delay chains were implemented in a 1-μm GaAs enhancement/depletion (E/D) process where the depletion-mode FETs (DFETs) and the enhancement-mode FETs (EFETs) have threshold voltages of -0.6 and 0.15 V, respectively, in order to obtain an experimental characterization of these gates. In addition, the TTDL gates were used to implement a 4-b carry-lookahead adder. The adder has a critical delay of 0.8 ns and a power dissipation of 130 mW     

Bipolar dynamic memory cell

A bipolar dynamic memory cell for use in a high-speed random- access memory consists of a cross-coupled pair of transistors and two diodes. Information is dynamically stored using a bistable charge distribution and must be refreshed at a frequency of 1 kHz by a SELECT operation. Standby power per memory cell is in the nanowatt range. The cell requires only 3 interconnect lines and can be fabricated with standard bipolar technology on 12-mil/SUP 2/ silicon area. Cycle time is limited by the speed of decoding, driving, and sensing circuits and is estimated to be 50 ns for a 512-bit RAM chip with complete on-chip decoding.     

A new low-power GaAs two-single-port memory cell

This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36×37 μm² using a 0.6-μm technology. An experimental 32 word × 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word×4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 μA/cell when operated at 1 V     

Design and performance of multistage GaAs dynamic logic

GaAs Two-Phase Dynamic FET Logic (TDFL) circuits are capable of extremely low power dissipation (20 nW/MHz/gate), high speed (1 GHz), and are compatible with static GaAs logic families. This paper demonstrates that TDFL can be modified to execute two or three stages of logic in one clock phase. This extension provides extremely high functional complexity per gate that can be used to reduce power dissipation, reduce latency, and increase circuit density in both sequential and computationally-oriented applications. The performance of these gates was demonstrated by E/D MESFET IC test circuits fabricated by a digital IC foundry. A one clock cycle, 8-b carry-lookahead adder operated at 350 MHz with only 1.1 mW of power dissipation     

Active GaAs sensor element for dynamic pressure measurements

A piezoelectric pressure sensor is presented which consists of a GaAs MESFET in which the transverse piezoelectric effect is used to charge the gate pad. The MESFET itself acts as an integrated charge amplifier. The sensor gives output signals which are comparable to those of a much bulkier commercial measurement system. The sensitivity achieved is 200 mV/bar in the range 0-20 bar     

Photoelectrical memory in GaAs/AlGaAs multilayer quantum-well structures

An increase in the dark current (by 2–3 orders of magnitude) in GaAs/Al_xGa_1−x As multilayer quantum-well structures with x⋍0.4 is observed after illumination of the structures with optical light (λ<1.3 μm). This increase is sustained for an extended time (more than 10³ s) at low temperatures. It then decreases to its initial value upon heating of the sample. A model of the barrier with local sag of the conduction band facilitating tunneling is proposed. The conduction band sag and the magnitude of the current grow due to optical ionization of uncontrolled deep level clusters present in the barrier and decrease due to subsequent capture of electrons from the conduction band by the deep levels upon heating. Fiz. Tekh. Poluprovodn. 32, 209–214 (February 1998)     

Electrical characterization of a JFET-accessed GaAs dynamic RAMcell

A complete one-transistor dynamic RAM cell in GaAs is discussed. Read and write operations is monitored by observing the capacitance of the storage node. Storage times on the order of a few seconds are obtained at room temperature with an activation energy slightly less than half the zero-temperature bandgap     

GaAs MESFET physical models for process-oriented design

A detailed physical model which is used to accurately predict the DC and microwave performance of GaAs MESFETs is described. This model, which accounts for hot electron effects in submicron FETs, includes trapping phenomena and heating due to power dissipation. It is used to determine the optimal design for small-signal and power devices, including single- and double-recessed FETs. The spread in device characteristics can be directly related to the variation in device geometry and process parameters experienced in fabrication. The accuracy and flexibility of this approach are demonstrated by comparison with measured data for a variety of devices     

Wavemaker in the design of GaAs MMICs

WaveMaker started out as a GaAs MMIC layout editing software package, to which was added a layout capture and schematic capture facility to enable the user to create netlist files in the Touchstone and Super Compact. The next step was to add the circuit simulator, and this has recently been completed with version 3.0 of WaveMaker.     

GaAs基辐射福特效应电池电极图案设计

研究了串并联电阻对太阳能电池和β伏特效应电池的影响, 并在此基础上提出了GaAs基β伏特效应电池的电极图案设计原则。在该原则的指导下设计了一批GaAs基PIN结的电极图案,测试了这些PIN结在⁶³Ni源辐照下的输出特性。与传统的梳状电极相比,本文电极设计可以降低对⁶³Ni辐射β粒子的反散射和阻挡作用,有效的增加了电池的输出电流,而这种电极设计不会对电池的开路电压,填充因子和理想因子带来不利的影响。     

Electrode pattern design for GaAs betavoltaic batteries

The sensitivities of betavoltaic batteries and photovoltaic batteries to series and parallel resistance are studied.Based on the study,an electrode pattern design principle of GaAs betavoltaic batteries is proposed.GaAs PIN junctions with and without the proposed electrode pattern are fabricated and measured under the illumination of ⁶³Ni.Results show that the proposed electrode can reduce the backscattering and shadowing for the beta particles from ⁶³Ni to increase the GaAs betavoltaic battery short circuit currents effectively but has little impact on the fill factors and ideal factors.     

Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FETlogic

Two-phase dynamic FET logic (TDFL) gates are used in GaAs MESFET MSI circuits to implement very low power 4-b ripple carry adders and a variable modulus (2 to 31) prescaler. Operation of the adders is demonstrated at 500 MHz with an associated power dissipation of less than 1.0 mW and at 750 MHz with P_d=1.7 mW. The prescaler, which contains 166 TDFL gates and 79 static gates, is shown to operate up to 850 MHz with an associated power dissipation of 9.2 mW from its 1.0-V supply. The operation of the adders and prescalers demonstrates the use of three- and four-input TDFL gates and a completely dynamic TDFL XNOR gate. The TDFL gates in these circuits dissipate only from 14 to 20 nW/MHz     

Design and application of a GaAs digital RF memory chip

The design and performance of a GaAs integrated memory/logic chip designed for digital RF memory (DRFM) applications is described. This chip, called a programmable delay-line element (PDLE), implements the basic DRFM storage and delay functions. The RAM-with-logic configuration combines a 4-kb static RAM with 750 logic gates, providing on a single chip the components for storage, address generation, demultiplexing, multiplexing, and control functions normally provided by a variety of separate chips. A distributed control organization, where the chip is configured to provide as outputs all the signals required as inputs to another identical chip, is used. Chips cascaded into strings implement the programmable delay lines required for DRFM systems. Problems associated with complex signal distribution networks are avoided since, within a string, signal distribution requires only local interconnections between adjacent chips. Correct operation of all functions was demonstrated in a four-chip string which provides a total memory capacity of 16 kb. The maximum sampling rate was 800 MHz, and power dissipation was approximately 2 W per chip     

A thermal-generation-limited buried-well structure for room-temperature GaAs dynamic RAM's

We report measurements of 200-s charge-recovery time constants at 300 K in the dark for an MBE-grown GaAs p- -n+ - p-buried well structure. Storage-time-versus-temperature measurements indicate that the charge recovery is due to generation through midgap levels. The results suggest the possibility of MODFET- or MESFET-compatible single-transistor buried-well dynamic RAM's capable of operating at or above room temperature.