A GaAs HBT 16×16 10-Gb/s/channel crosspoint switch

A 16×16 crosspoint switch IC has been designed and implemented in a 2-μm GaAs heterojunction bipolar transistor (HBT) technology. The IC is a strictly nonblocking switch with broadcast capability and asynchronous data paths. The IC has fully differential internal circuitry and is packaged in a custom high-speed assembly. Test results confirmed that the IC achieves a 10-Gb/s/channel (or 160-Gb/s aggregate) capacity, the highest reported to date for a 16×16 crosspoint switch IC     

A 10-Gb/s high-isolation, 16×16 crosspoint switch implementedwith AlGaAs/GaAs HBT's

A high-isolation, 16×16 crosspoint switch is reported, capable of aggregate data throughput of 160 Gb/s with low crosstalk and output jitter. Each of the 16 fully asynchronous channels can transmit data at rates up to 10 Gb/s with a worst case r.m.s. output jitter of 4 ps. Single channel operation output jitter below 2.8 ps r.m.s. has been demonstrated. The high-isolation circuitry allows for inter-channel crosstalk isolation of more than 40 dB with all channels operative. The circuit is based on AlGaAs/GaAs heterojunction bipolar transistor technology     

A 70-Mbit/s (RZ) 16×16 crosspoint switch for ternary-encodedsignals

An experimental 16×16 crosspoint switch that can switch ternary signals and handle data rates of up to 70 Mb/s return-to-zero (RZ) (equivalent to 140-Mb/s nonreturn-to-zero (NRZ)) per channel is described. Ternary signals, in particular, alternate mark inversion (AMI) encoded signals, are widely used in telephone interoffice digital-transmission systems. This chip could be used in an asynchronous cross-connection system at the DS3 (44.736-Mb/s) signal level. This crosspoint chip has 16 input and 16 output channels. Any input can be connected to any output or outputs without blocking. The architecture allows for paralleling many chips to increase the size of the crosspoint array and also for cascading them to provide multistage switching capability. The switch can be addressed in the same way as a memory chip, and the cross-connection map can be written to and read back from the device. The chip is fabricated using a standard 2-μm CMOS technology, and the die size is 20.16 mm² (177.2×176.4 mil), containing about 11000 transistors     

A 16×16 crosspoint switch for ternary encoded signals

A crosspoint-switching chip that can switch bipolar, alternate mark inversion encoded (AMI) signals directly, is described. AMI encoding is a form of ternary, return-to-zero (RZ) coding where a binary zero is represented by an absence of a pulse and ones are represented with an alternating sequence of positive and negative pulses. Bipolar signals are used widely in interoffice telecommunications such as the T1, T1C, T2, and T3 digital transmission systems. The switching chip has 16 input and 16 output channels. Control of the chip allows any input to be connected to any output or outputs, providing a nonblocking connection. The architecture allows for expansion of the crosspoint array by paralleling several chips. The chip, fabricated using a standard 3-μm CMOS technology, is capable of handling data rates up to 15 Mb/s per channel, has about 17000 transistors, and has an area of about 32.5 mm²     

A 9.5-Gb/s Si-bipolar ECL array

A 9.5-Gb/s Si-bipolar ECL array that has a gate delay of 35 ps, a risetime of 45 ps, and a falltime of 40 ps is described. The ECL circuit design and the chip layout were optimized. A Si-bipolar process with 0.3-μm emitter width and packaging capable of accepting 10-GHz signal were used. The array was used in three key circuits of an optical communication system: a decision circuit, a 4:1 multiplexer, and a 1:4 demultiplexer. Operation of the decision circuit at 9.5 Gb/s, of the 4:1 multiplexer at 6.7 Gb/s, and of the 1:4 demultiplexer at 6.7 Gb/s were confirmed     

16×20-Gb/s, 400-km WDM transmission over NZDSF using aslope-compensating fiber-grating module

We demonstrate 16-channel wavelength-division multiplexing transmission over nonzero dispersion-shifted fiber at a per-channel rate of 20 Gb/s. A broad-band dispersion-compensating grating module is used for compensation of dispersion and dispersion slope     

A 250-Mb/s 32×32 CMOS crosspoint LSI for ATM switchingsystems

A 32×32 crosspoint LSI and a time-slot controlled asynchronous-transfer-mode (ATM) switch architecture utilizing the LSI are presented. The ATM switch, which is classified as an input-buffer-type ATM switch, enables 99% throughput and broadcasting capability. The crosspoint LSI is characterized by the bit-map oriented and pipelined connection control method which can switch and broadcast 160-Mb/s ATM cells, 32×32 switch cells which have less parasitic capacitance, and emitter-coupled-logic (ECL) compatible interfaces which are compatible with a 160-MHz broadband ISDN data rate. The LSI has been fabricated by a 1-μm CMOS process. The chip size is 7.4 mm×7.4 mm. According to the evaluation, operation at 250 Mb/s is confirmed. 1.2-W power consumption is observed at 160-Mb/s operating condition     

A 16×622 Mb/s ATM switch: PRELUDE switch architectureintegrated into a 6-million transistor monochip

This paper presents the integration of the Prelude switch architecture into a monochip ATM switch, COM16M, capable of handling 16 multiplexes carrying ATM cells at 622 Mb/s. It is a fully autonomous switch, i.e., the chip includes clock adaptation, routing, and cell buffering as well as header translation and control capabilities. The switch is integrated into one single chip containing 6000000 transistors implemented in a 0.5-μm CMOS process     

Advanced architecture for a one-chip 16×16 digital switch

A one-chip 16×16 digital switch (SWEL) is presented which is designed for use in a wide variety of applications, ranging from digital mobile radio and satellite applications, to PCM switching systems (integrated services digital network). It provides a compact, low-power solution to perform in channel-controlled switching of 64-kb/s or 2-Mb/s channels. Both architecture and design issues are discussed in detail; a 1.2 μm double metal CMOS technology was employed in the design. The multiplexed architecture allows for easy implementation of new application-specific requirements, making this circuit the cornerstone for new telecommunication switching products     

16×16 optical-fiber crossbar switch operating at 0.85 μm

An optical-fiber crossbar switch has been constructed using fully integrated GaAs optoelectronic receivers, custom monolithic GaAs laser drivers, and an electrical 32×32 silicon crossbar switch. 470 Mb/s operation has been achieved with a bit error rate of less than 10^-12. The approach uses a monolithic GaAs optoelectronic integrated receiver to convert optical signals into electrical signals that are fed into an Si 32×32 electronic crossbar switch. The switch outputs are used to drive laser transmitters consisting of a custom monolithic GaAs IC laser driver and a 0.85 μm GaAs/AlGaAs laser. The system could be reconfigured in 1 μm, limited by the control logic, with the switch chip capable of reconfiguration in 35 ns. No errors are induced by reconfiguration     

A 2×2 crosspoint switch fabricated on the passive activeresonant coupler (PARC) platform

We demonstrate the fabrication of a 2×2 crosspoint switch monolithically fabricated on the passive active resonant coupler (PARC) platform by utilizing vertical resonant coupling over a taper between an active and a passive waveguide. The coupling taper was 100 μm long with less than 0.15 dB coupling loss. By pushing the mode up and down as and when required, we are able to integrate passive waveguides and electroabsorption modulators on one chip. The static performance of the switch has been tested, and a modulation depth of 30 dB has been achieved at the wavelength of 1.57 μm for an applied bias of 2.5 V     

168-Gb/s all-optical wavelength conversion with asymmetric-Mach-Zehnder-type switch

Error-free all-optical wavelength conversion at 168 Gb/s, which is the highest repetition rate ever reported, has been achieved by using a symmetric-Mach-Zehnder (SMZ)-type switch. Low-power-penalty 84-Gb/s operation is also demonstrated. The push-pull switching mechanism of the SMZ switch enables such ultrafast operation based on cross-phase modulation associated with the carrier depletion in a semiconductor optical amplifier. The configuration of the delayed-interference signal-wavelength converter, which is a simplified variant of the SMZ switch, is used in this experiment     

Low-loss and high-extinction-ratio silica-based strictlynonblocking 16×16 thermooptic matrix switch

A low-loss and high-extinction-ratio silica-based 16×16 thermooptic matrix switch is demonstrated. The switch, which employs a double Mach-Zehnder interferometer switching unit and a matrix arrangement which reduces the total waveguide length, is fabricated with 0.75% refractive index difference waveguides on a 6-in silicon wafer. The average insertion loss and the average extinction ratio are 6.6 and 55 dB, respectively. The total power consumption is 17 W     

A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs

An 8×8 and an expandable 16×16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10^-9 at 2.5 Gb/s using a 2⁹-1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8×8 LSI and 2.8 W for the expandable 16×16 LSI     

40-Gb/s OTDM to 4×10 Gb/s WDM conversion in monolithic InPMach-Zehnder interferometer module

Transformation of high bit-rate optical time-domain multiplexed (OTDM) signals into a multitude of lower bit-rate wavelength-division-multiplexed (WDM) channels is demonstrated by means of a single monolithically integrated indium phosphide Mach-Zehnder interferometer with semiconductor optical amplifiers in its arms. Full demultiplexing of 10-Gb/s OTDM signals into 4×10-Gb/s WDM channels is demonstrated. Bit-error-rate penalties are below 1.5 dB for polarization independent signal conversion throughout the 1.55-μm wavelength range     

A 5-Gb/s OEIC with voltage-up-converter

In this paper (based on our previous paper at ESSCIRC 2004, "A 2.4 GHz-Bandwidth OEIC with Voltage-Up-Converter," but new results for 4 Gb/s and 5 Gb/s have been added), an optoelectronic integrated circuit (OEIC) with an integrated voltage-up-converter (VUC) to enhance the frequency response of an integrated pin photodiode is presented. With the VUC a voltage of 11 V is generated on the chip without any additional external components. Thus, for a single-supply environment of 5 V the bandwidth of the OEIC is increased from 1.5 to 2.4 GHz. For data rates of 1, 3, 4, and 5 Gb/s at a bit error rate of 10/sup -9/, sensitivities of -29.3, -24.3, -22.9, and -20.5 dBm, respectively, were measured at a wavelength of 660 nm. For the implementation of the OEIC a modified 0.6-/spl mu/m silicon BiCMOS technology with f/sub T/=25 GHz is used.     

A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO

An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6-μm high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm×4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s     

DPSK 32×10 Gb/s transmission modeling on 5×90 kmterrestrial system

Reduction of DWDM nonlinear fiber penalties by the use of DPSK modulation and an optically preamplified self-homodyning receiver is discussed. Maintaining a constant instantaneous channel power by phase shift keying, we can anticipate reduction of cross-phase modulation penalties. Our modeling results show 0.9-dB benefit in Q performance for 50-GHz spaced, 32×10 Gb/s transmissions with nonzero dispersion shifted fiber     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

5 V, 10 Gbit/s optical receiver module using Si-bipolar IC

A 10 Gbit/s optical receiver module using a Si-bipolar IC has been developed. For low power and low cost, a pure Si-bipolar IC is used in place of a GaAs IC, which is commonly used for over 10 Gbit/s. To widen the frequency bandwidth, multifeedback techniques and a two-stage buffer configuration are used in the preamplifier IC. In addition, a differential circuit configuration is used for stable operation at high frequency. The IC was fabricated using 0.25 μm Si-bipolar technology. The module exhibits sensitivity of <-16 dBm for 10 Gbit/s data with an input dynamic range >15 dB. Small power consumption of 410 mW is achieved with the single power-supply voltage of +5 V