A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power

A millimeter-wave power amplifier fabricated in 90 nm bulk CMOS technology consists of 3 identical cascode stages and on-chip matching networks (inter-stage, input, and output) implemented with wide-gap coplanar waveguides and M6-M5 (MIM) capacitors. The amplifier realizes a linear power gain of 19.7 dB at 52.4 GHz and 10.3 dB at 60 GHz. Maximum saturated output power and output-referred compression point are and 3.1 dBm, respectively. Peak PAE is 4.2%. The 1.180.96 die consumes 75 mA when operating from a 2 V supply.     

A 60 GHz SiGe-HBT Power Amplifier With 20% PAE at 15 dBm Output Power

A monolithic power amplifier (PA) operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 SiGe-heterojunction bipolar transistor (HBT) technology, featuring npn transistors with and . A two-stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a small signal gain of 18.8 dB and an output power of 14.5 dBm under 1 dB gain compression at 61 GHz. At this frequency, the saturated output power is 15.5 dBm and the peak power added efficiency (PAE) is 19.7%. To our knowledge, this is the highest PAE reported so far for a monolithic 61 GHz PA in SiGe-HBT technology.     

A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control

A + 20 dBm power amplifier (PA) for applications in the 60 GHz industrial scientific medical (ISM) band is presented. The PA is fabricated in a 0.13-mum SiGe BiCMOS process technology and features a fully-integrated on-chip RMS power detector for automatic level control (ALC), built-in self test and voltage standing wave ratio (VSWR) protection. The single-stage push-pull amplifier uses center-tapped microstrips for a highly efficient and compact layout with a core area of 0.075 mm². The PA can deliver up to 20 dBm, which to date, is the highest reported output power at mm-wave frequencies in silicon without the need for power combining. At 60 GHz it achieves a peak power gain of 18 dB, a 1-dB compression (P1dB) of 13.1 dBm, and a peak power-added efficiency (PAE) of 12.7%. The amplifier is programmable through a three-wire serial digital interface enabeling an adaptive bias control from a 4-V supply.     

一种-30 dBm射频能量收集整流器

基于高频整流与匹配放大的方法,采用标准0.18 μm CMOS工艺,设计了一种接收信号频率可调的无线射频能量收集整流器。通过调节匹配网络中的片外可调电感,实现了不同频段无线信号的有效接收与放大,并提供一种高效的射频整流技术,大幅降低最小接收信号强度,增大了系统的接收灵敏度。仿真实验结果表明:当无线信号为915 MHz时,系统的接收灵敏度达到-30 dBm,输出直流电压为2.1 V;无线接收信号为2.4 GHz时,系统的接收灵敏度达到-24 dBm,输出直流电压为2.4 V。     

射频功率放大器

介绍了中波广播发射机中射频功率放大器的组成,工作原理和效率分析,以及其维护、维修的要点,并对比实际电路做刨析。     

A 18 GHz Broadband Stacked FET Power Amplifier Using 130 nm Metamorphic HEMTs

A broadband power amplifier (PA) with a 3 dB power bandwidth of 72% is presented using metamorphic high electron mobility transistors (mHEMTs). A stacked FET structure, where transistors are series connected to combine voltage swings, is employed to overcome relatively low breakdown voltages of mHEMTs. Series-connected PA's show much higher load impedance compared to the parallel combined transistors, which allows output matching to be realized in the low quality (Q)-factor region, providing the broadband performance. The fabricated PA using quadruple-stacked 130 nm mHEMTs has a gain of 21.2 dB and saturated output power of 26.4 dBm with power added efficiency (PAE) of 33% at the design frequency of 18 GHz. The 3 dB output power bandwidth is from 10 to 23 GHz.      

A 60-W Multicarrier WCDMA Power Amplifier Using an RF Predistorter

In this brief, we present a 60-W power amplifier that is linearized using an RF predistorter for multicarrier wideband code-division multiple-access (WCDMA) applications. The proposed RF predistorter is fully composed of RF or analog circuits, and it has a moderate memory effect compensation capability using a delayed third-order intermodulation (IM3) component path. It also includes the IM5 generation circuits and a compact IM3 generator that is capable of autocanceling for the fundamental component. The proposed RF predistorter was implemented and applied to a 60-W high-power WCDMA amplifier. For a four-carrier downlink WCDMA signal, the RF predistorter improved the adjacent channel leakage power ratio at a 5-MHz offset by 6.19 dB at an average output power of 48 dBm. The total efficiency of the system is as high as 13.6% at the same output power level. At an output power level of 60 W, the linearized power amplifier complies with the linearity specification of the WCDMA system.     

A Linear Power Amplifier Design Using an Analog Feedforward Method

We propose and describe the fabrication of a linear power amplifier (LPA) using a new analog feedforward method for the IMT‐2000 frequency band (2,110–2,170 MHz). The proposed analog feedforward circuit, which operates without a pilot tone or a microprocessor, is a small and simple structure. When the output power of the fabricated LPA is about 44 dBm for a two‐tone input signal in the IMT‐2000 frequency band, the magnitude of the intermodulation signals is below ?60 dBc and the power efficiency is about 7%. In comparison to the fabricated main amplifier, the magnitude of the third intermodulation signal decreases over 24 dB in the IMT‐2000 frequency band.     

基于 SiGe 工艺的线性功率放大器设计

基于SiGe Heterojunction Bipolar Transistors（HBT）工艺设计了一款线性射频功率放大器．该功率放大器采用三级级联结构,每一级采用自适应偏置网络,级间匹的网络集成在片内,匹配网络中的电感由绑定线实现．该功率放大器工作在2G Hz ,带宽50M Hz ,增益30dB ,在1dB压缩点输出功率（P1dB ）为27．1dBm ,功率附加效率（PAE）为36％．该功放由3．4V电压供电,芯片尺寸1mm ×0．7mm ．     

60 G Hz 11 dBm CMOS功率放大器设计

近年来60 GHz附近的一个连续频段可以自由使用,这为短距离的无线个域网等高速率传输的应用提供了条件.设计了一个工作在60 GHz的CMOS功率放大器.采用台积电0.13μmRF-CMOS工艺设计制造,芯片面积为0.35mm × 0.4 mm,最大线性输出功率为11 dBm,增益为9.7 dB,漏极增加效率(η_(PAE))为9.1%.达到应用在通信距离为10 m的无线个域网(WPAN)射频电路中的要求.设计中采用了厚栅氧化层工艺器件和Load-Pull方法设计最优化输出阻抗z_(opt),以提高输出功率.该方法能较大提高CMOS功率放大器的输出功率,可以应用到各种CMOS功率放大器设计中.     

一种温度不敏感的高线性功率放大器

设计了一种温度不灵敏的高线性度的射频功率放大器芯片,采用新颖的带温度反馈环路的有源片上自适应偏置电路,该电路降低了温度引起的放大器集电极直流电流分量的变化量,补偿了由温度变化而引起的性能偏差,进而有效提高了放大器的线性度。基于这个温度不灵敏的偏置结构采用InGaP/GaAs HBT工艺设计了一个工作在2110~2170 MHz频段的功率放大器。测试结果表明,该功放在工作频段内的增益大于等于35.3 dB;在中心频率2140 MHz处,1 dB功率压缩点大于33 dBm,功率附加效率在输出功率24.5 dBm时为18%;使用LTE_FDD调制信号,获得邻信道功率比为-47 dBc。在环境温度为-40℃、+25℃和+80℃条件下,功放的增益平坦度较好,增益变化量小于1.5 dB,输出级集电极电流基本不变,有效降低了功放对温度的敏感性。     

基于MHVIC2115的射频功率放大器设计

采用MHVIC2115器件设计一个WCDMA驱动级放大器.采用SIP数据模型对输出匹配电路进行仿真设计,解决了器件电路模型无法获取问题.通过添加电位器,减少栅极偏置电路供电端口,方便下一步测试.对于底面源极接地,采用金属支座来承载器件,而非通过焊盘上的过孔来接地.该方法既改善了源极的导电、导热性,又方便了器件的安装固定.     

高效率线性RF功放的研究与设计

应用EER(Envelope Elimination and Restoration)线性功放技术和高效率D类音频放大技术,实现了一个高效率线性RF功率放大器。该线性放大器为AM调制,7MHz时效率优于75％。     

一种20 W音频功率放大器

介绍了一种20 W音频功率放大器专用电路的工作原理及其电路与版图设计.该电路在音频放大应用中具有低失真度的高性能,能够在电源电压士25 V的条件下为4 Q或8 Q的负载提供20 W的功率输出.该电路设计采用了先进的线路结构,保证了大功率输出时的低失真度,同时具有高增益、高速、宽带、大输出摆幅、大输出电流和大电源电压范围等特点.     

线性化Doherty功率放大器的研究

阐述了线性化功率放大器的发展过程。利用ADS进行Doherty功放的仿真分析,设计了一种多个放大器并联的Doherty功放电路,并与经典的Doherty功放比较效率的高低。研究结果表明,此多级并联Doherty功放电路比传统功率放大器效率要高,并且有电路简单、成本低、工作稳定等优点。     

2.45 GHz高线性功率放大器设计

基于SMIC 0.18 μm RF-CMOS工艺,实现了一种工作于2.45 GHz的功率放大器,给出了电路仿真结果和电路版图.电路采用两级放大的结构,分别采用自偏置技术和电阻并联负反馈网络来缓解CMOS器件低击穿电压的限制,同时保证了稳定性的要求.为了提高线性度,采用一种集成的二极管线性化电路对有源器件的输入电容变化提供一种补偿机制,漏端的LC谐振网络和优化的栅偏置用来消除由跨导产生的非线性谐波.在3 V电源电压下,放大器功率增益为23 dB,输出1 dB压缩点约为25 dBm,对应的功率附加效率PAE可达35%.     

应用于移动终端的线性功率放大器设计

设计了一种应用于移动终端的InGaP/GaAs HBT功率放大器。该放大器采用了一种新颖的在片偏置电路技术,不仅避免了由于电源和温度变化导致的直流偏置点的不稳定,而且补偿了由于输入信号增大所引起的动态偏置点的偏离。电流镜结构的偏置电路与反馈电路使偏置电压维持在一个稳定的状态,在反馈电路中引入一个非反相电路加强了电路增益。通过在偏置管的基极并联一个反偏二极管改善了功率放大器的线性。芯片采用基板的封装形式进行测试,改善了功率放大器的散热条件。测试结果表明该放大器具有27.6 dBm的输出压缩点,对于W-CDMA应用,放大器的效率为34.1%,ACPR为-40.3 dBc。     

一种新型自适应偏置线性功率放大器

为了改善常用电压偏置功率放大器对偏置电压、温度和工艺的敏感影响,提出了一种新型的低耦合自适应偏置电路结构,并采用改进的负载牵引仿真方法,通过在Jazz SiGe BiCMOS 0.35μm工艺上的设计实现表明,最大线性功率可以有效地提高2dB,效率可以提高12.5%.工作在2.4 GHz频段上的此功率放大器可以适用于蓝牙增强数据率模式和无线局域网802.11b/g等采用线性调制的发送端.     

A Ku-Band Interference-Rejection CMOS Low-Noise Amplifier Using Current-Reused Stacked Common-Gate Topology

A Ku-band CMOS low-noise amplifier (LNA) with high interference-rejection (IR), wide gain control range, and low dc power consumption is presented. The LNA consists of two common-gate metal-oxide-semiconductor field-effect transistors interconnected with an interstage parallel tank for the IR. The stacked common-gate stages share the same dc bias current to reduce power consumption and have controllable gain by changing this dc current. The implemented 0.13 mum CMOS LNA achieves measured power gain of 10.8 dB, noise figure of 4.2 dB, output P₁ dB of -4.3 dBm at 15 GHz, while rejecting interference down to a 38.5 dB level. The gain control range is 23.3 dB by varying the gate voltage from 0.2 to 1.2 V. The LNA consumes only 4 mA from a 1.3-V supply.