A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

A 18 GHz Broadband Stacked FET Power Amplifier Using 130 nm Metamorphic HEMTs

A broadband power amplifier (PA) with a 3 dB power bandwidth of 72% is presented using metamorphic high electron mobility transistors (mHEMTs). A stacked FET structure, where transistors are series connected to combine voltage swings, is employed to overcome relatively low breakdown voltages of mHEMTs. Series-connected PA's show much higher load impedance compared to the parallel combined transistors, which allows output matching to be realized in the low quality (Q)-factor region, providing the broadband performance. The fabricated PA using quadruple-stacked 130 nm mHEMTs has a gain of 21.2 dB and saturated output power of 26.4 dBm with power added efficiency (PAE) of 33% at the design frequency of 18 GHz. The 3 dB output power bandwidth is from 10 to 23 GHz.      

High Efficiency Linear Power Amplifier for IEEE 802.11g WLAN Applications

This letter presents the power amplifier (PA) design for IEEE 802.11g WLAN applications by using InGaP/GaAs heterojunction bipolar transistors (HBTs) with the dual bias network as the linearizer to improve the output power capability and linearity. The final designed PA utilizes a 3.3-V supply voltage producing a good power-aided-efficiency (PAE) in 39.3% with 26.5-dBm output power and 18.1-dB gain for a 2.4-GHz OFDM/64-QAM stimulus, while the error vector magnitude (EVM) is maintained at 4.9%, satisfying the standard specifications.     

A 60 GHz SiGe-HBT Power Amplifier With 20% PAE at 15 dBm Output Power

A monolithic power amplifier (PA) operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 SiGe-heterojunction bipolar transistor (HBT) technology, featuring npn transistors with and . A two-stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a small signal gain of 18.8 dB and an output power of 14.5 dBm under 1 dB gain compression at 61 GHz. At this frequency, the saturated output power is 15.5 dBm and the peak power added efficiency (PAE) is 19.7%. To our knowledge, this is the highest PAE reported so far for a monolithic 61 GHz PA in SiGe-HBT technology.     

A Highly Efficient and Linear Class-AB/F Power Amplifier for Multimode Operation

The class-AB/F power amplifier (PA), a multimode PA, which can operate at both class-AB and class-F modes, is analyzed and compared with the conventional class-F and class-AB PAs. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. To demonstrate the multimode PA, the PA is implemented using an InGaP/GaAs HBT process and it is tested with reverse-link IS-95A code division multiple access (CDMA) and PCS1900 global system for mobile communications signals in the personal communications service band. The class-AB operation for a CDMA signal delivers a power-added efficiency (PAE) of 38.9% and an adjacent channel power ratio of 49.5 and 56.5 dBc at the offset of 1.25 and 2.25 MHz, respectively, at the output power of 28 dBm. The maximum PAE of 64.7% under the class-F operation is measured at 32.5-dBm output power for a GSM signal. The class-AB/F PA is a good candidate for the multimode PA of next-generation wireless communication systems.     

A novel full-wave rectifier/sinusoidal frequency doubler topology based on CFOAs

In this paper, a high-efficiency class-F power amplifier (PA) is designed using integration between a low voltage p-HEMT transistor and a miniaturized microstrip suppressing cell. It results in nth harmonic suppression and high power added efficiency (PAE) under low radio frequency (RF) input powers. The simulation is performed based on harmonic balance analysis. The proposed power amplifier is fabricated, and measurements results validated the simulations. The proposed power amplifier operates at 1.8 GHz with 100 MHz bandwidth and an average PAE of 71.1%, with very low drain voltage of 2 V. At fundamental frequency of 1.8 GHz, the maximum measured PAE is 73.5% at about 12 dBm RF input power. The maximum output power and gain are 23.4 and 17.5 dBm in RF input power ranges of 0–12 dBm, respectively. The fabricated class-F PA with such characteristics can be used for power amplifications in wireless transmitters such as 4G (4th generation)-LTE (long term evolution) communication systems.     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.     

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.     

High Efficiency RF Power Amplifier Designed With Harmonic Real-Time Active Load-Pull

In this work, a high efficiency p-HEMT radio frequency power amplifier (PA) is designed using a new multiharmonic real-time active load-pull using the large signal network analyzer. This technique synthesizes a large set of instantaneous load mismatches to quickly find the optimal harmonic impedances, so as to achieve high PA efficiency in a shortened design cycle. At 2 GHz a demo power amplifier implemented with a p-HEMT demonstrated a power added efficiency (PAE) of 68.5% for 18.0 dBm output power, while achieving a maximum PAE of 75% below the 1 dB compression point for 18.6 dBm output power.     

17-GHz 50-60 mW power amplifiers in 0.13-/spl mu/m standard CMOS

Two versions of power amplifiers with different output matching approaches for the 17-GHz band were realized in 0.13-/spl mu/m standard digital CMOS technology with 1.5-V supply voltage. The power amplifier with an external matching network delivers 17.8-dBm saturated output power with 15.6% power added efficiency (PAE). The small-signal gain is 11.5 dB. The fully integrated power amplifier delivers 17.1-dBm saturated output power with 9.3% PAE. The small-signal gain is 14.5 dB. No external radio frequency components are required.     

Effects of output harmonic termination on PAE and output power of AlGaN/GaN HEMT power amplifier

The authors experimentally investigate and discuss the effects of output harmonic termination on power added efficiency (PAE) and output power of an AlGaN/GaN high electron mobility transistor (HEMT) power amplifier (PA). The AlGaN/GaN HEMT PA with gate periphery of 1 mm was built and tested at L-band. Large-signal measurements and comparisons of the PAE and output power were carried out at different DC bias conditions from 50% of saturated drain current (I/sub dss/) to 1% of Id., for the PA with and without output harmonic termination. For class-AB operation at 25% of I/sub dss/, an increase of about 10% in peak PAE and 1 dBm in output power were observed in saturated output power range. Improvements of up to 9% in PAE and 1.2 dBm in output power were achieved over the measured DC bias conditions provided the output harmonics are properly terminated.     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

Analysis and design of high-power and efficient,millimeter-wave power amplifier systems using zero degree combiners

We present the analysis and design of high-power millimetre-wave power amplifier (PA) systems using zero-degree combiners (ZDCs). The methodology presented optimises the PA device sizing and the number of combined unit PAs based on device load pull simulations, driver power consumption analysis and loss analysis of the ZDC. Our analysis shows that an optimal number of N-way combined unit PAs leads to the highest power-added efficiency (PAE) for a given output power. To illustrate our design methodology, we designed a 1-W PA system at 45 GHz using a 45 nm silicon-on-insulator process and showed that an 8-way combined PA has the highest PAE that yields simulated output power of 30.6 dBm and 31% peak PAE.     

高效率GaAs/InGaAsHFET功率放大器

研制成 Ga As/ In Ga As异质结功率 FET(HFET) ,该器件是在常规的高 -低 -高分布 Ga As MESFET的基础上 ,在有源层的尾部引入 i-In Ga As层。采用 HFET研制的两级 C波功率放大器 ,在 5 .0～ 5 .5 GHz带内 ,当Vds=5 .5 V时 ,输出功率大于 3 2 .3 1 d Bm(0 .1 77W/ mm ) ,功率增益大于 1 9.3 d B,功率附加效率 (PAE)大于3 8.7% ,PAE最大达到 49.4% ,该放大器在 Vds=9.0 V时 ,输出功率大于 3 6.65 d Bm(0 .48W/ mm) ,功率增益大于 2 1 .6d B,PAE典型值 3 5 %     

A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V

This paper describes circuit design and measurement results of our newly developed InGaP/GaAs-HBT MMIC power amplifier (PA) module which can operate with 2.4-V low reference and low supply voltages of its on-chip bias circuits. To achieve the low-reference voltage operation, the following two new circuit design techniques are incorporated into the power amplifier: 1) AC-coupled, divided power stage configuration with two different kinds of bias feeding (voltage and current drive and only current drive) and 2) successful implementation of a diode linearizer built in the power stage. Theses two techniques allow the PA to offer smooth output transfer characteristics over a wide temperature range. Measurement results done under the conditions of 900 MHz, a 3.5-V collector voltage for power stage, and 2.4-V reference and collector voltages for the bias circuits show that the PA module meets J-/W-CDMA power and distortion requirements sufficiently over a wide temperature range from -10degC to 90degC while keeping a low quiescent current of less than 65 mA. For J-CDMA modulation, the module can deliver a 27.5-dBm output power (P_out), a 40% PAE, and a -50-dBc ACPR, while a 28-dBm P_out, a 42% PAE, and a -42-dBc ACLR are achieved for W-CDMA modulation.     

A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control

A + 20 dBm power amplifier (PA) for applications in the 60 GHz industrial scientific medical (ISM) band is presented. The PA is fabricated in a 0.13-mum SiGe BiCMOS process technology and features a fully-integrated on-chip RMS power detector for automatic level control (ALC), built-in self test and voltage standing wave ratio (VSWR) protection. The single-stage push-pull amplifier uses center-tapped microstrips for a highly efficient and compact layout with a core area of 0.075 mm². The PA can deliver up to 20 dBm, which to date, is the highest reported output power at mm-wave frequencies in silicon without the need for power combining. At 60 GHz it achieves a peak power gain of 18 dB, a 1-dB compression (P1dB) of 13.1 dBm, and a peak power-added efficiency (PAE) of 12.7%. The amplifier is programmable through a three-wire serial digital interface enabeling an adaptive bias control from a 4-V supply.     

A balanced FET FMCW radar transceiver with improved AM noiseperformance

A balanced FET frequency-modulated continuous-wave radar transceiver designed to suppress AM noise is presented. The transceiver utilizes the same device for output power amplification as for down-conversion of the received signal, thereby avoiding the need for separation of these signals. This makes the transceiver suitable for integration in monolithic-microwave integrated-circuit technology. A test circuit operating at 10 GHz was designed. The AM noise suppression is characterized, as well as output power and noise performance. Comparison with an unbalanced transceiver using the same principle of operation shows an improvement of 20 dB in AM noise performance. The output power is 14 dBm at 7-dBm input power     

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P_{1 dB} of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P_{1 dB} of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.     

A 2.4-GHz SiGe HBT power amplifier with bias current controlling circuit

A 2.4-GHz SiGe HBT power amplifier (PA) with a novel bias current controlling circuit has been realized in IBM 0.35-μm SiGe BiCMOS technology, BiCMOS5PAe. The bias circuit switches the quiescent current to make the PA operate in a high or low power mode. Under a single supply voltage of 3.5 V, the two-stage mode-switchable power amplifier provides a PAE improvement up to 56.7% and 19.2% at an output power of 0 and 20 dBm, respectively, with a reduced quiescent current in the low power mode as compared to only operating the PA in the high power mode. The die size is only 1.32 × 1.37 mm2.