Interface profile optimization in novel surface passivation scheme for InGaAs nanostructures using Si interface control layer

This paper attempts to control and optimize the interface atomic profiles of a novel surface passivation scheme for InGaAs nanostructures, using a silicon interface control layer (ICL). An in-situ x-ray photoelectron spectroscopy characterization technique was used to establish a process sequence that satisfies the conditions of maintenance of pseudomorphic matching to InGaAs, prevention of direct oxidation of InGaAs, and formation of a good SiO₂/Si interface with minimal suboxide components. It is shown that the above conditions can be satisfied by a new process that is a formation of the thermal SiO₂ at the SiO₂-Si interface by repetition of deposition/oxidation/annealing cycle. A large reduction of interface state density (N_ss) was realized by the optimization of the new process, resulting in a minimum N_ss of 4 × 10¹¹ cm⁻² eV⁻¹. The silicon ICL technique was successfully applied to the passivation of InGaAs wire structures.     

Comparison of MOS capacitors on n- and p-type GaN

The electrical characteristics of both n- and p-type GaN metal-oxide semiconductor (MOS) capacitors utilizing plasma-enhanced CVD-SiO₂ as the gate dielectric were measured. Both capacitance and conductance techniques were used to obtain the MOS properties (such as interface state density). Devices annealed at 1000°C/30 min. in N₂ yielded an interface state density of 3.8×10¹⁰ cm⁻² eV⁻¹ at 0.19 eV from the conduction band edge, and it decreased to 1.1×10¹⁰ cm⁻² eV⁻¹ deeper into the band gap. A total fixed oxide charge density of 8×10¹² q cm⁻² near the valence band was estimated. Unlike the symmetric interface state density distribution in Si, an asymmetric interface state density distribution with lower density near the conduction band and higher density near the valence band was determined.     

Characterization of physical and electrical properties of BaTiO<Subscript>3</Subscript> films deposited on p-Si by modified polymeric precursors

Highly uniform BaTiO₃ (BTO) films with thickness well below 100 nm were deposited on p-Si by spin coating using a modified polymeric precursor method. The polymeric precursor gel was redissolved into glacial acetic acid to improve the wetting property of the spinning solution to the Si substrates (2.5-in. diameter). The morphology, composition, thickness, and refractive index of the films were investigated using x-ray diffraction (XRD), scanning electron microscopy (SEM), energy-dispersive x-ray spectroscopy (EDS), and ellipsometry. The films are found to be polycrystalline. They exhibit uniformity over the whole wafer in regard to thickness, composition, and absence of surface features. The capacitors constructed with the BTO films on Si were further investigated by electrical characterizations. Current-voltage (I-V) measurements reveal a leakage current due to a Poole-Frenkel mechanism. The energy gap is evaluated to be 3.95 eV. A metal-insulator-semiconductor (MIS) behavior is observed through capacitance-conductance-voltage (C-G-V) measurements. The interface state density (D_it) at the BTO/p-Si interface is estimated to be of the order of 10¹² eV⁻¹ cm⁻².     

STUDY OF THE ANODIZATION OF Al FILM ON InP SUBSTRATE AND ITS PROPERTIES

The anodization of Al film on InP substrate and properties of anodic Al_2O_33/InPhave been investigated by AES,DLTS,I-V,C-V and ellipsometer.The results show that theanodic oxide Al_2O_3 has a permittivity of 11～12 and a resistivity of 1.3×10~(13) ohm-cm.Interfacestate density at Al_2O_3/InP is about 10~(11) cm~(-2)·eV~(-1).DLTS reveals that there is a continuouslydistributed interface electron traps at Al_2O_3/InP interface.Anodic Al_2O_3 exhibits good stabilityand electrical properties and could be used for passivation,diffusion mask and gate insulator,etc.     

Effect of epilayer characteristics and processing conditions on the thermally oxidized SiO2/SiC interface

The optimization of the SiO₂/SiC interface is critical for the development of SiC MOS devices. We investigate the effects of several variables spanning both epilayer attributes and processing conditions relative to our control oxidation process. Varying the shallow vicinal angle of the wafer does not affect the interface. There is a definite degradation of the interface as the epilayer doping density is increased. Sacrificial oxidation appears to reduce the number of border traps in the final oxide. Fluorine annealing has no effect on the interface quality. A low temperature (950°C) re-oxidation, which follows a bulk oxide growth at 1150°C, reduces D _it to the mid-10¹⁰ cm⁻²eV⁻¹ range near midgap and Q_f to a reacord low 5×10¹¹ cm⁻².     

Characteristics of Si3N4/GaAs metal-lnsulator-semiconductor interfaces with coherent Si/Al0.3Ga0.7As interlayers

Si₃N₄/GaAs metal-insulator-semiconductor (MIS) interfaces with Si(10Å)/ Al_0.3Ga_0.7As (20Å) interface control layers have been characterized using capacitance-voltage (C-V) and conductance methods. The structure was in situ grown by a combination of molecular beam epitaxy and chemical vapor deposition. A density of interface states in the 1.1 × 10¹¹ eV^-1 cm^-2 range near the GaAs midgap as determined by the conductance loss has been attained with an ex situ solid phase annealing of 600°C in N₂ ambient. A dip quasi-static C-V demonstrating the inversion of the minority-carrier verifies the decent interface quality of GaAs MIS interface. The hysteresis and frequency dispersion of the MIS capacitors were lower than 100 mV, some of them as low as 50 mV under a field swing of about ±2 MV/cm. The increase of the conductance loss at higher frequencies was observed when employing the surface potential toward conduction band edge, suggesting the dominance of faster traps. Self-aligned gate depletion mode GaAs metal-insulator-semiconductor field-effect transistors with Si/Al_0.3Ga_0.7As interlayers having 3 μm gate lengths exhibited a transconductance of about 114 mS/mm. The present article reports the first application of pseudomorphic Si/ Al_0.3Ga_0.7As interlayers to ideal GaAs MIS devices and demonstrates a favorable interface stability.     

Effects of post-annealing on the passivation interface characteristics of AlGaN/GaN high electron mobility transistors

We examined the effects of post-annealing in forming-gas ambient on the spin-on-dielectric (SOD)-buffered passivation as well as the conventional plasma-enhanced chemical vapor deposition (PECVD) Si₃N₄ passivation structure in association with the quantitative analysis of defects at the passivation interfaces of AlGaN/GaN high electron mobility transistors (HEMTs). Before the annealing, the interface state densities (D_it) of the PECVD Si₃N₄ are one-order higher (10¹²–10¹³ cm⁻² eV⁻¹) than those of the SOD SiO_x (10¹¹–10¹² cm⁻² eV⁻¹) as derived from C–V characterization. Clear reduction in D_it from the PECVD Si₃N₄ is extracted to a level of 10¹¹–10¹² cm⁻² eV⁻¹ with a stronger absorption from Si–N peak in Fourier transform infrared spectroscopy spectra after the post-annealing. On the other hand, negligible difference in D_it value is obtained from the SOD SiO_x. In this paper we propose that much lower measurement levels (~156 mA/mm) before the annealing and substantial recovery (~13% increase) after the annealing in maximum drain current density of the AlGaN/GaN HEMTs with Si₃N₄ passivations are due to the original higher density before the annealing and greater reduction in D_it of the PECVD Si₃N₄ after the annealing. Significant reduction after the annealing in gate–drain leakage current (from ~10⁻³ to ~10⁻⁵ A, 100-μm gate width) of the HEMTs with the Si₃N₄ passivation is also supposed to be attributed to the reduction of D_it.     

Influence of substrate temperature on the properties of fluorinated silicon-nitride thin films deposited by IC-RPECVD

Fluorinated silicon-nitride films have been prepared from an Ar/SiF₄/NH₃ gas mixture by inductively coupled remote plasma-enhanced chemical vapor deposition (IC-RPECVD) at different substrate temperatures, ranging from 150 to 300°C. All of the resulting deposited silicon-nitride films were free of Si-H bonds, showed high dielectric breakdown fields (≥8 MV cm^?1), and had root mean square (rms) surface roughness values below 3 Å. The films’ refractive indices and the contents of O and F remain constant, but Si/N ratios drop from 5 to 2 and N-H bond concentrations decrease in the range (1.3–0.9) × 10²² cm^?3 as the substrate temperature increases. The density of interface states (D_it) with c-Si was reduced from 2.4 × 10¹² to 8 × 10¹¹ eV^?1 cm^?2 at substrate temperatures ≥250°C.     

Effect of processing conditions on inversion layer mobility and interface state density in 4H−SiC MOSFETs

N-channel, inversion mode MOSFETs have been fabricated on 4H−SiC using different oxidation procedures, source/drain implant species and implant activation temperature. The fixed oxide charge and the field-effect mobility in the inversion layer have been extracted, with best values of 1.8×10¹² cm⁻² and 14 cm²/V-s, respectively. The interface state density, D_it close to the conduction band of 4H−SiC has been extracted from the subthreshold drain characteristics of the MOSFETs. A comparison of interface state density, inversion layer mobility and fixed oxide charges between the different processes indicate that pull-out in wet ambient after reoxidation of gate oxide improves the 4H−SiC/SiO₂ interface quality.     

Effect of GaAs surface pretreatment on electrical properties of MBE-ZnSe/GaAs substrate interfaces

Interface properties of MBE-grown ZnSe/GaAs substrate systems formed on variously pretreated GaAs surfaces, which include standard chemically etched (5H₂SO₄:1H₂O₂: 1H₂O), (NH₄)₂S_x-, NH₄I-, and HF-pretreated surfaces, are investigated by capacitance-voltage (C-V) and deep level transient spectroscopy (DLTS) measurements. A HF-pretreated and annealed ZnSe/p-GaAs sample showed marked reduction of interface state density, N_ss, with N_ss,_min below 4 x 10¹¹cm^-2 eV^-1 near E_c- E_FS= 1.0 eV. The value is about one order of magnitude smaller than that of the standard chemically etched interface, and comparable to (NH₄)₂S_x- pretreated interface. Nevertheless, C-V characteristics of ZnSe/nGaAs samples, which were measured for the first time, indicate that interface Fermi level, E_FS, is not completely unpinned due to the interface states located above the midgap. A consistent result was obtained by DLTS method in determining E_FS position. The influence of N_ss distribution on vertical current conduction is also analyzed. It is found that U-shaped interface states with N_ss(E) > 1 x 10¹³ cm^-2 eV^-1 above the midgap may cause an excess voltage drop larger than a few volts at the interface.     

MeV energy sulfur implantation in GaAs and InP

Room temperature and elevated temperature sulfur implants were performed into semi-insulating GaAs and InP at variable energies and fluences. The implantations were performed in the energy range 1–16 MeV. Range statistics of sulfur in InP and GaAs were calculated from the secondary ion mass spectrometry atomic concentration depth profiles and were compared with TRIM92 values. Slight in-diffusion of sulfur was observed in both InP and GaAs at higher annealing temperatures for room temperature implants. Little or no redistribution of sulfur was observed for elevated temperature implants. Elevated temperature implants showed higher activations and higher mobilities compared to room temperature implants in both GaAs and InP after annealing. Higher peak electron concentrations were observed in sulfur-implanted InP (n ≈ 1 × 10¹⁹ cm⁻³) compared to GaAs (n ≈ 2 × 10¹⁸ cm⁻³). The doping profile for a buried n⁺ layer (n ≈ 3.5 × 10¹⁸ cm⁻³) of a positive-intrinsic-negative diode in GaAs was produced by using Si/S coimplantation.     

New plasma chemistries for etching III–V compound semiconductors: Bl3 and BBr3

We investigated inductively coupled plasma (ICP) etching of both In-containing (InP, InAs, and InSb) and Ga-containing compound semiconductors (GaAs, GaP, and GaSb) in two new chemistries: BI₃ and BBr₃ with addition of Ar. Etch rates as high as 2 μm·min⁻¹ were obtained for InP in both types of discharge while for GaAs maximum rates were 1 and 2.5 μm·min⁻¹, respectively, in BI₃ and BBr₃. The rates were strongly dependent on plasma composition, ICP source power and radio frquency chuck power. BI₃ etching produced much smoother surfaces on both GaAs and InP, while maintaining the near-surface stoichiometry. Etch selectivities ≥ 10 were obtained for GaAs and InP over SiO₂ and SiN_x masks. The BI₃ chemistry appears attractive as an universal etchant for In-based and Ga-based compound semiconductors.     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

Growth and characterizations of InP self-assembled quantum dots embedded in InAIP grown on GaAs substrates

We report the characteristics of InP self-assembled quantum dots embedded in In_0.5Al_0.5P on GaAs substrates grown by metalorganic chemical vapor deposition. The InP quantum dots show increased average dot sizes and decreased dot densities, as the growth temperature increases from 475°C to 600°C with constant growth time. Above the growth temperature of 600°C, however, dramatically smaller and densely distributed self-assembled InP quantum dots are formed. The small InP quantum dots grown at 650°C are dislocation-free “coherent” regions with an average size of ∼20 nm (height) and a density of ∼1.5 × 10⁸ mm⁻². These InP quantum dots have a broad range of luminescence corresponding to red or organge in the visible spectrum.     

Improved electrical properties on the anodic oxide/InP interface for MOS structures

The interface properties of the anodic oxide/n-type (111) InP metal oxide semiconductor (MOS) structures significantly improved while using the polishing agent HBr:K₂Cr₂O₇:H₂O (BCA). Annealing at 250°C dehydrates the grown oxides and has a strong effect on the surface potential. Composition of the oxides analyzed using x-ray photoelectron spectroscopy showed that the oxides are composed of In₂O₃, InPO₃, and InPO₄. MOS structures fabricated on BCA polished substrates show a lower surface state density of 6 × 10¹⁰ cm⁻² eV⁻¹ when compared to the substrates polished with bromine-methanol (8 × 10¹⁰ cm⁻² eV⁻¹).     

Low temperature passivation of Si1−xGex alloys by dry high pressure oxidation

Thermal passivation of Si_1−xGe_x using high pressure (70 MPa) oxidation was studied for potential use in MOS-device applications. Alloys of CVD-grown Si_1−xGe_x (x = 10 and 15 at.%, 200 and 150 nm thick, respectively), were oxidized at 500 and 550°C using high purity dry oxygen at a pressure of 70 MPa. For comparative purposes, a second set of alloys were oxidized using conventional wet atmospheric pressure oxidation at 800°C. X-ray photoelectron spectroscopy (XPS), Raman spectroscopy, transmission electron microscopy (TEM), and metal-oxide semiconductor capacitance-voltage (C-V) measurements were used to characterize the as-grown oxides. Chemical analysis by XPS confirmed that under high pressure conditions compositionally congruent oxides are grown from these alloys. High resolution TEM and Raman spectroscopy show that the as-grown oxide/semiconductor interface is planar and free of Ge enrichment on a scale of 1-2 monolayers. A midgap interface state density for both the 10 and 15 at.% samples of 1 × 10¹² cm⁻² eV⁻¹ was estimated based on 1 MHz C-V measurement.     

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS2 Field‐Effect Transistors

2D materials are promising to overcome the scaling limit of Si field‐effect transistors (FETs). However, the insulator/2D channel interface severely degrades the performance of 2D FETs, and the origin of the degradation remains largely unexplored. Here, the full energy spectra of the interface state densities (D_it) are presented for both n‐ and p‐ MoS₂ FETs, based on the comprehensive and systematic studies, i.e., full rage of channel thickness and various gate stack structures with h‐BN as well as high‐k oxides. For n‐MoS₂, D_it around the mid‐gap is drastically reduced to 5 × 10¹¹ cm^?2 eV^?1 for the heterostructure FET with h‐BN from 5 × 10¹² cm^?2 eV^?1 for the high‐k top‐gate. On the other hand, D_it remains high, ≈ 10¹³ cm^?2 eV^?1, even for the heterostructure FET for p‐MoS₂. The systematic study elucidates that the strain induced externally through the substrate surface roughness and high‐k deposition process is the origin for the interface degradation on conduction band side, while sulfur‐vacancy‐induced defect states dominate the interface degradation on valance band side. The present understanding of the interface properties provides the key to further improving the performance of 2D FETs.     

The properties of photo chemical-vapor deposition SiO<Subscript>2</Subscript> and its application in GaN metal-insulator semiconductor ultraviolet photodetectors

High-quality SiO₂ insulating layers were successfully deposited onto GaN by a photo chemical-vapor deposition (photo-CVD) technique using a deuterium (D₂) lamp as the excitation source. The interface-trap density, D_it, was estimated to be 8.4×10¹¹ cm⁻²eV⁻¹ for the photo-CVD SiO₂ layers prepared at 300°C. It was found that the leakage current was only 6.6×10⁻⁷ A/cm² with an applied field of 4 MV/cm for the 300°C photo-CVD-grown Al/SiO₂/GaN metal-insulator semiconductor (MIS) capacitor. It was also found that the photo-CVD SiO₂ layer could be used to suppress the dark current of nitride-based photodetectors. A large photocurrent to dark-current contrast ratio higher than three orders of magnitude and a maximum 0.12 A/W responsivity were observed from the fabricated indium tin oxide (ITO)/photo-SiO₂/GaN MIS ultraviolet (UV) photodetectors. Furthermore, it was found that corresponding noise-equivalent power (NEP) and normalized detectivity, D*, of our ITO/photo-SiO₂/GaN MIS UV photodetectors was 2.19×10⁻⁹ W and 2.03 × 10⁸ cmHz_0.5W⁻¹, respectively, for a given bandwidth of 500 Hz.     

Growth and characterization of inTISb for IR-detectors

Epitaxial In_1-xTl_xSb films with compositions up to x = 0.1 have been demonstrated using the metalorganic chemical vapor deposition technique on InSb and GaAs substrates. A specially designed high-temperature source delivery system was used for the low vapor pressure cyclopentadienylthallium source. Tl-compositions in the deposited films were measured by Rutherford backscattering spectroscopy which confirmed the incorporation of up to 10% Tl. Room temperature infrared transmission spectra of InTISb exhibited considerable absorption beyond 7 μm. Photoconductive detectors were fabricated in InTISb films grown on semi-insulating GaAs. Spectral response measurements showed substantial photoresponse at 8.5 to 14 μm. In spite of the large lattice-mismatch (≈14%) between InTISb and GaAs, photoconductive detectors exhibited black-body detectivities (D^* _bb) of 5.0 × 10⁸ cm-Hz^1/2W⁻¹ at 40K.     

Investigations on Au,Ag, and Al schottky diodes on liquid encapsulated czochralski grown n-GaAs〈100〉

The Schottky barrier heights of metals Au, Ag, and Al fabricated by vacuum vapor deposition on liquid encapsulated Czochralski (LEC) grown undoped ntype GaAs (n = 2.35 × 10¹⁵ cm⁻³) were measured with current-voltage (I-V) and capacitance-voltage (C-V) techniques. Good ohmic contacts were obtained through an after deposition anneal at 430°C for two minutes in an argon gas atmosphere. In the as-deposited state, Au, Ag, and Al gave very similar I-V characteristics for n-type substrates with the barrier height qϕ_b = 0.81-1.16 eV and ideality factor n = 1.02-1.15. The C-V measurement also gives the same value of barrier height. The distribution of carrier concentration along the radial distance of the wafer is of‘M’ shape. The Al/GaAs interfaces give the nonideal rectification behavior. The Au/GaAs interfaces give the near ideal rectification behavior. The barrier height of this interface is 0.89-0.92 eV and the ideality factor is about 1.10–1.19. Electron traps in the wafer have been found by constant capacitance deep level transient spectroscopy (CC-DLTS). Mainly the EL2, EL6, and EL3 (EI1) trap levels are prominent.