芯片叠层封装的失效分析和热应力模拟

通过高温高湿加速实验对双芯片叠层封装器件的失效进行了研究,观察到存在塑封料与上层芯片、BT基板与塑封料或贴片胶的界面分层和下层芯片裂纹等失效模式.结合有限元分析对器件内热应力分布进行了计算模拟,分析了芯片裂纹的失效机理,并从材料性能和器件结构角度讨论了改善叠层封装器件可靠性的方法.     

浅析环氧塑封料性能与器件封装缺陷

简要介绍了环氧塑封料可靠性、流动性、内应力等性能及影响因素：对环氧塑封料与铜框架失效机理进行了分析,包括试验方法等内容,并对封装器件中产生的气孔、油斑问题,从环氧塑封料性能改进方面作了分析,这些都是为了保证最后成品的质量和可靠性,另外对其他器件封装缺陷也作了简要叙述．     

夹层式叠层芯片引线键合技术及其可靠性

随着电子封装技术的快速发展,叠层封装成为一种广泛应用的三维封装技术,该技术能够满足电子产品高性能、轻重量、低功耗、小尺寸等日益增长的需求。针对陶瓷封装腔体中的夹层式叠层芯片结构,键合点与键合引线处于陶瓷外壳空腔中,未有塑封料填充固定,区别于塑封叠层芯片封装器件,优化其引线键合技术,并做了相应可靠性评估试验。键合引线偏移长度最大为0.119 mm,未出现键合引线间隙小于设计值、碰丝短路等情况,为高可靠叠层芯片封装研究提供了参考。     

塑封器件回流焊与分层的研究

由于无铅焊料的应用,回流焊的温度提高影响了塑封器件的质量和可靠性。针对实际的LQFP器件,利用有限元软件建立三维模型,分析了塑封器件在潮湿环境中的湿气扩散及回流焊中的形变和热应力分布,并讨论了塑封料参数及细小裂纹对分层的影响。结果表明,在湿热的加载下,塑封器件的顶角易发生翘曲现象;芯片与塑封料界面处易分层,导致器件失效。     

3D叠层封装集成电路的芯片分离技术

3D叠层封装是高性能器件的一种重要的封装形式,其鲜明的特点为器件的物理分析带来了新的挑战.介绍了一种以微米级区域研磨法为主、化学腐蚀法为辅的芯片分离技术,包括制样方法及技术流程,并给出了实际的应用案例.该技术实现了3D叠层芯片封装器件内部多层芯片的逐层暴露及非顶层芯片中缺陷的物理观察分析,有助于确定最终的失效原因,防止失效的重复出现,对于提高集成度高、容量大的器件的可靠性具有重要的意义.     

叠层CSP芯片封装热应力分析与优化

对四层叠层CSP（SCSP）芯片封装器件,采用正交试验设计与有限元分析相结合的方法研究了芯片和粘结剂——8个封装组件的厚度变化在热循环测试中对芯片上最大热应力的影响．利用极差分析找出主要影响因子并对封装结构进行优化。根据有限元模拟所得结果．确定了一组优选封装结构,其Von Mises应力值明显比其它组低,提高封装器件的可靠性。     

超声波清洗引入的芯片金属化裂纹机理分析

对某塑封器件进行破坏性物理分析(DPA),发现芯片表面存在玻璃钝化层裂纹和金属化层划伤的缺陷。对缺陷部位进行扫描电子显微镜(SEM)检查和能谱(EDS)分析,通过形貌和成分判断其形成原因为开封后的超声波清洗过程中,超声波振荡导致环氧塑封料中的二氧化硅填充颗粒碰撞挤压芯片表面,从而产生裂纹。最后,进行了相关的验证试验。研究结论对塑封器件的开封方法提出了改进措施,对塑封器件的DPA检测及失效分析(FA)有一定借鉴意义。     

芯片叠层封装工艺技术研究

随着大量电子产品朝着小型化、高密度化、高可靠性、低功耗方向发展,将多种芯片封装于同一腔体内的芯片叠层封装工艺技术将得到更为广泛的应用,其封装产品的特点就是更小、更轻盈、更可靠、低功耗。芯片叠层封装是把多个芯片在垂直方向上堆叠起来,利用传统的引线封装结构,然后再进行封装。芯片叠层封装是一种三维封装技术,叠层封装不但提高了封装密度,降低了封装成本,同时也提高了器件的运行速度,且可以实现器件的多功能化。随着叠层封装工艺技术的进步及成本的降低,多芯片封装的产品将更为广泛地应用于各个领域,覆盖尖端科技产品和应用广大的消费类产品。     

叠层QFN器件界面层裂失效研究

为了探究造成微电子封装器件界面层裂的根源,选取了叠层QFN器件进行建模仿真,模拟了其在热加载条件下的器件应力分布情况。通过粘结强度实验,测出加载力与位移的关系,其中力的峰值为2.52N,裂纹开口位移为0.29mm,计算得到的界面断裂能为10.5N/m。采用内聚力模型(CZM)与J积分这两种数值预测方法,对芯片粘结剂与铜引脚层界面层裂失效作了研究,找到裂纹萌生的关键点;两者对裂纹扩展趋势的结论一致,在预测裂纹产生方面,CZM法比J积分法更方便。     

高功率密度电源模块磁芯粘接的工艺可靠性

新型高功率密度电源模块采用芯片塑封的工艺方式,实现磁芯、元器件、印制板(PCB)和塑封料的一体式封装.磁芯设计采用绕组内置在印制板内部,并采用扁平磁芯装配的方式实现磁芯的电气功能.由于磁芯材料、粘接材料和印制板之间的材料性能不匹配,环境试验中产生的粘接内应力过大会直接造成磁芯材料产生裂纹甚至断裂失效,严重影响了电源产品...     

多芯片叠层封装中的芯片应力分析及结构优化

针对典型的四层芯片叠层封装产品,采用正交试验设计与有限元分析相结合的方法研究了芯片、粘合剂、顶层芯片钝化层和密封剂等十个封装组件的厚度变化对芯片上最大热应力的影响,并利用找到的主要影响因子对封装结构进行优化.结果表明,该封装产品可以在更低的封装高度下实现,并具有更低的芯片热应力水平及更小的封装体翘曲,这有助于提高多芯片叠层封装产品的可靠性.     

功率载荷下叠层芯片封装的热应力分析和优化

应用有限元分析软件ANSYS,模拟功率载荷下叠层芯片封装中芯片温度和应力分布情况,得出芯片的温度、应力与材料厚度、热膨胀系数之间的关系,根据分析,对模型进行了优化.优化后的模型最高温度下降了3.613 K,最大应力下降了33.4%,最大剪应力下降了45.9%.     

叠层芯片封装技术与工艺探讨

论述了在叠层芯片封装的市场需求和挑战。首先采用在LQFP一个标准封装尺寸内,贴装2个或更多的芯片,这就要求封装体内每一个部分的尺寸都需要减小,例如芯片厚度、银胶厚度,金丝弧度,塑封体厚度等,要求在叠层封装过程中开发相应的技术来解决上述问题。重点就芯片减薄,银胶控制,无损化装片,立体键合,可靠性等进行了详细的介绍。     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

Packaging parameter analysis and optimization design on solder joint reliability for twin die stacked packages by variance in strain energy density (SED) of each solder joint

In accordance with vigorous development of the electronic product market as well as the consumers’ preference for smaller scales, the structure of 3D stacked die package rapidly becomes popular. Hereafter the stacked process of the silicon dies always makes the coupling effect among materials more complicated. Such an issue has been seriously paid attention to and becomes a critical problem to be solved for the product reliability. In this paper, the ANSYS software is adopted to analyze a twin die stacked package under a cyclic thermal loading condition. The viscoplastic finite element analysis and the Darveaux theory are applied to investigate the solder joint reliability (SJR) of the stacked die package. This research will verify a significant dependence between the solder joint fatigue life of the stacked die package and the distribution of the accumulated strain energy density (SED) on the solder joints by proposing a viewpoint of the variance of the strain energy density among solder joints for a 3D-Slice model.     

多目标优化方法在叠层QFN封装结构优化中的应用

文章采用响应曲面法试验设计与有限元仿真相结合的方法对叠层QFN封装器件在热循环条件下进行仿真分析,通过优化结构参数来降低叠层QFN封装在热循环条件下的Von Mises应力和封装翘曲。使用多目标优化设计方法中的统一目标法来综合考虑Von Mises应力和封装翘曲。应用遗传算法对评价函数在约束条件下进行搜索最优解,得出叠层QFN封装结构优化的方案,以提高封装的可靠性。     

SCSP中芯片黏结层在焊接时的可靠性

提出了一个细观力学模型,该模型同时考虑了热膨胀和蒸汽膨胀对叠层芯片尺寸封装(SCSP)中芯片黏结层变形的影响.当初始温度确定时,由该模型可求得给定温度下芯片黏结层内部的蒸汽压力和孔隙率,从而判断芯片黏结层在焊接回流时的可靠性.当温度从100℃升高到250℃时,芯片黏结层的饱和蒸汽压、等效弹性模量及孔隙率分别从0.10 ...     

一款系统级封装产品设计及失效分析

文中以一款两颗芯片、一颗压力传感器及一颗谐振器的集成封装为例,研究了堆栈芯片、PCB与引线框架粘结、长线弧键合、异质材料粘合等封装中的常见问题的解决方法,提出了优化设计方案。使用DOE试验找出各个工序的最佳参数,设计工艺流程,并使用生产设备制造出样品,验证了封装设计的可制造性及设计可靠性。对样品进行失效分析,找出设计中存在的不足,提出解决方案。