Microwave frequency crosstalk model of redistribution line patterns on wafer level package

As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer S-parameter measurements and was fitted to the measurements made at up to 5 GHz.     

Modelling of coupled interconnect lines for integrated circuits

A coupled interconnect model is developed using even mode and odd mode capacitance analysis. Signal coupling is presented in terms of interconnect width, substrate thickness, interconnect line spacing, and frequency. Picosecond photoconductor based measurements of coupled transmission lines on the integrated circuit support the even and odd mode signal transmission simulation results. SPICE circuit simulation is used to demonstrate the model utility and explore the sensitivity of the self- and mutual capacitances and inductances in signal crosstalk.     

Modeling of interconnect capacitance, delay, and crosstalk in VLSI

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations     

Full-wave modelling and broadband characterization of coupled interconnects in high-speed VLSI

A time-domain full-wave method for the extraction of broadband equivalent circuit parameters of symmetrical coupled interconnection lines on chips is presented. This method is based on the two-dimensional finite-difference time-domain method. After determination of the even and odd mode propagation constant γ and characteristic impedance Z _c of the lines, the RLGC matrices per unit length can be obtained. Many techniques are proposed and used during the time-domain analysis to improve the efficiency. The circuit parameters extracted can be inserted into circuit simulation software to investigate the time-domain responses of high-speed integrated circuits on chips. The reliability of this method is verified by its applications to typical problems.     

A better technique using multisegment modeling and analysis of high-density and high-speed connectors

A useful and rather new simulation technique for connectors up to 6.25 GHz is presented and discussed in this paper. The proposed model extracts electrical parameters of a connector using time-domain reflectometry (TDR) measurements. A new technique was developed to obtain accurate impedance profiles using TDR and a multisegment approach that is effectively a distributed coupled model. The parameter extraction and characterization of connectors are discussed. The performance of the proposed segmented transmission line model is verified by simulation of the model in SPICE and by experimental measurement. The results show that the proposed model can simulate the electrical characteristics, including crosstalk and impedance, of high-density and high-speed connectors with satisfactory accuracy. Based on the proposed modeling and CAD simulators, the design and analysis of complicated high-density and high-speed connectors can be executed accurately and effectively. Compared with other previous models, the proposed model can significantly improve the accuracy of simulation.     

Twisted differential line structure on high-speed printed circuit boards to reduce crosstalk and radiated emission

Differential signaling has become a popular choice for high-speed digital interconnection schemes on printed circuit boards (PCBs), offering superior immunity to crosstalk and external noise. However, conventional differential lines on PCBs still have unsolved problems, such as crosstalk and radiated emission. When more than two differential pairs run in parallel, a line is coupled to the line adjacent to it because all the lines are parallel in a fixed order. Accordingly, the two lines that constitute a differential pair are subject to the differential-mode crosstalk that cannot be canceled out by virtue of the differential signaling. To overcome this, we propose a twisted differential line (TDL) structure on a high-speed multilayer PCB by using a concept similar to a twisted pair in a cable interconnection. It has been successfully demonstrated by measurement and simulation that the TDL is subject to much lower crosstalk and achieves a 13-dB suppression of radiated emission, even when supporting a 3-Gb/s data rate.     

A time-domain full-wave extraction method of frequency-dependentequivalent circuit parameters of multiconductor interconnection lines

A time-domain full-wave method for the extraction of frequency-dependent equivalent circuit parameters of multiconductor interconnection lines is presented in this paper. The circuit parameters extracted by this method can be inserted into circuit simulation software to investigate time-domain responses of a high-speed IC system with multiconductor interconnects. Because the definitions of the voltage and the current are not unique in full-wave analysis, transformation among circuit parameters according to different definitions of the voltage and current is also presented. The method is based on the finite-difference time-domain (FDTD) method, and the reliability of this method is illustrated by its application to representative problems     

High-frequency SPICE model of anisotropic conductive film flip-chipinterconnections based on a genetic algorithm

This paper firstly reports on the high-frequency SPICE model of the ACF flip-chip interconnections up to 13 GHz. The extraction process is based on an optimization procedure, called a genetic algorithm, which is known as a robust optimization tool. The proposed equivalent circuit model of the ACF interconnection can readily be used in SPICE circuit simulations for signal integrity analysis of high-frequency packages. Two different ACF interconnections were studied using the Au-coated polymer ball and Ni-filled ball. The extracted models of the two ACFs were found strongly dependent on not only size and rigidity of the conducting balls, but also on their magnetic permeability     

微米级平行互连线的测试结构设计

研究分析无串扰传输理想模型的条件,根据高速高密度电路板中微米级、亚毫米级互连线电磁串扰特性研究需要,首次提出微米级平行互连线的测试结构设计。经射频电路理论分析推导了测试结构对系统串扰没有影响。构建了有、无测试结构的微米级平行互连线物理模型,仿真分析后,加工制作有测试结构的微米级平行互连线电路板。研究结果表明,当数字基带信号传输频率在0~3 GHz 范围时,无测试结构仿真电路模型、有测试结构仿真电路模型、有测试结构的实验电路板,三者串扰特性吻合;微米级平行互连线的测试结构设计合理,具有工程参 考价值。     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Analysis and modeling of multilevel parallel and crossing interconnection lines

Analytical and numerical techniques to study the pulse propagation characteristics such as delay, distortion, and crosstalk in multilevel interconnections associated with high-speed digital IC's including VLSI chips are presented. The parallel and crossing interconnections at various levels are modeled as lossy coupled lumped distributed parameter systems, which are analyzed for their time domain characteristics. The characterizing electrical parameters of the structures are computed by utilizing the network analog method that has been formulated to solve for the lossy line constants and parasitic coupling associated with a three-dimensional multiconductor system in a layered lossy medium. It is shown that the time domain response of the multiport structures can be computed by using standard CAD programs such as SPICE by utilizing compatible circuit models developed from the solution of such systems. Examples of the step and pulse response of typical systems are included to demonstrate the versatility, usefulness, and accuracy of the techniques presented in the paper.     

Analysis of 3-D interconnect structures with PEEC using SPICE

This paper discusses the possibilities of using the circuit simulation program, simulation program with integrated circuit emphasis (SPICE) for the simulation of partial element equivalent circuit (PEEC) models. After an introduction into the PEEC method, the simulation of quasi-stationary models is considered. An enhancement of SPICE is described, allowing the simulation of retarded PEEC models. This enables the computation of electric fields radiated from an interconnection structure. With the modified SPICE simulator it is possible to use existing SPICE models and combine them with full wave PEEC models     

深亚微米VLSI电路中互连线的几何优化设计

基于三维 L aplace方程的 Silvaco Interconnect3D模拟程序数值解 ,对互连寄生电容进行了计算 ,其结果用于 0 .2 5μm CMOS技术互连延迟及串扰的 SPICE模拟中。模拟结果表明 ,基于W/ P=0 .3～ 0 .4的布线准则可以获得最优的互连延迟与串扰 (Crosstalk)特性 ,通过优化互连线及驱动管的几何尺寸可以显著地减小互连线的延迟及串扰噪声。     

Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz.     

太赫兹平面肖特基二极管参数模型

根据太赫兹平面肖特基二极管物理结构,在理想二极管SPICE参数模型的基础上建立了二极管小信号等效电路模型。依据该二极管等效电路模型设计了基于共面波导（CPW）去嵌方法的二极管S参数在片测试结构,并对其在0.1~50 GHz、75~110 GHz频率范围内进行了高频小信号测试,利用测试结果提取了高频下二极管电路模型中各部分电容、电阻以及电感参数。将相应的高频下电容与电阻参数分别与低频经验公式电容值和直流I-V测试提取的电阻值进行了对比,并利用仿真手段对高频参数模型进行了验证。完整的参数模型以及测试手段相较于理想二极管SPICE模型和传统的参数提取方法可以更为准确地表征器件在高频下的工作状态。该建模思路可用于太赫兹频段非线性电路的优化设计。     

Extraction of high-frequency equivalent circuit parameters ofsubmicron gate-length MOSFET's

As the effective gate-length of a MOSFET reduces, its high-frequency characteristics improve. However, they become more difficult to model. Current SPICE models are based on DC measurement data and simplistic capacitance models which can only approximate the high-frequency device characteristics up to a fraction of the device unity current gain frequency (f_τ). Thus, it is important to investigate the high-frequency characteristics and then incorporate the small-signal equivalent circuit parameters in SPICE. In this, work we report a simple nonquasi static model, which offers good accuracy needed for circuit simulation, and a new curve fitting method for the extraction of the network model elements. The current work is part of a study aimed at improving the existing scalable model for MOSFET's, and it focuses on extracting the elements of an equivalent circuit which describes the state-of-the-art device     

非平行微带线间的串扰抵消研究

非平行微带线是印刷电路板(PCB)上不可避免的互连结构。针对PCB 上非平行微带线间的串扰问题,用平行微带线近似非平行微带线,把平行耦合微带线间的串扰抵消方法应用到非平行耦合微带线中,提出了利用耦合传输线信道传输矩阵方法来进行远端串扰抵消,在对非平行耦合传输线信道传输矩阵进行特征值分解的基础上构建串扰抵消电路。仿真了非平行微带线间夹角分别为q=3°、5°、10°时的串扰,结果表明,该方法可以有效改善非平行微带线上信号眼图的质量,串扰抵消效果良好。     

Microwave frequency interconnection line model of a wafer level package

In this paper, we introduce the microwave transmission characteristics of interconnection lines on a wafer level package (WLP) and also propose a precise microwave-frequency model of the WLP interconnections. The slow wave factor (SWF) and attenuation constant are measured and discussed. High-frequency measurement is described, based on two-port S-parameter measurements, using an on-wafer microwave probe with a frequency range of up to 5 GHz. The extracted model is represented in the form of distributed lumped circuit model elements and can be easily merged into SPICE simulations. From the extracted model, it was found that line capacitance and inductance per unit length are 0.110 pF/mm and 0.286 nH/mm, respectively. We have successfully applied the extracted model to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, it was found that the WLP has better high-frequency performance, because of its low package inductance, compared with the /spl mu/BGA package, but longer propagation delay, because of the relatively high package capacitance.     

A new parameter extraction technique for small-signal equivalentcircuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz