Reducing Test Time Using an Enhanced RF Loopback

This work presents a method to improve the loopback test used in RF transceivers. The approach is targeted to the System-On-Chip environment, being able to reuse system resources in order to minimize the test overhead. An RF sampler is used during loopback operation, allowing observation of spectral characteristics of the RF signal. While able to improve the overall observability of the RF signal path, faster diagnosis than conventional loopback tests is achieved thanks to a large reduction in the number of transmitted symbols. Theoretical analysis and practical results for a prototype transceiver operating at 846 MHz are presented. It is shown that a significant test time reduction is achievable considering bit error rate tests for common digital modulation schemes.

BIST/Digital-Compatible Testing of RF Devices Using Distortion Model Fitting

Testing of Radio Frequency (RF) circuits for nonlinearity specifications generally requires the use of multiple test measurements thereby contributing to increased test cost. Prior RF test methods have suffered from significant test calibration effort (training for supervised learners) when using compact tests or from increased test time due to direct specification measurement. On the other hand, due to aggressive technology scaling, there are plenty of digital transistors available that can be used to simplify testing of Analog/Mixed-Signal (AMS) and RF devices. In this paper, an RF test methodology is developed that: (a) allows RF devices to be tested for several distortion specifications using distortion model fitting algorithms in test time comparable to what can be achieved using supervised learning techniques while retaining the accuracy of direct specification measurement, (b) allows multiple RF specifications to be determined concurrently from a single data acquisition and (c) allows digital-compatible testing/BIST to be performed using digital testers or on-chip built in self-test (BIST) circuitry. With regard to (a), a key benefit is that no training of supervised learning algorithm is necessary. The proposed method based on distortion model fitting is shown to give excellent results across common RF performance metrics while providing ~10× improvements in test time compared to previous methods.     

CMOS blocks for on-chip RF test

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.     

An On-Chip Loopback Block for RF Transceiver Built-In Test

This brief addresses the realization of an on-chip block for built-in testing of RF transceivers with the loopback method. Design issues and measurement results are discussed, giving practical insights into closing the signal path between transmitter (Tx) and receiver (Rx) sections. The circuit is intended for cost-efficient production testing of RF front-end blocks with on-chip power detectors and bit-error-rate analysis at baseband frequencies for integrated transceivers operating in the 1.9- to 2.4-GHz range. It can provide 40-200 MHz Tx-Rx frequency shifting and 26-42 dB continuous attenuation while consuming a 0.052-mm² die area in 0.13-mum CMOS technology and ~ 12 mW of power when activated in test mode.     

固态有源相控阵雷达射频系统一体化近场测试

本文介绍了一种固态有源相控阵雷达射频系统(含天线、馈线、发射、接收分系统)微波暗室的一体化测试方法,可以大大提高固态有源相控阵雷达测试的工作效率并且具有较高的精度与可信度。     

A full duplex 1200/300 bit/s single-chip CMOS model

The design of a Bell 212A (AT&T) compatible single-chip modem is described, and measured results are presented. The IC(Fairchild /spl mu/A212A) contains all signal-processing functions and supports all operating modes, including test modes and selection of either 1200 bit/s QPSK or 300 bit/s FSK operation. The modem offers such features as a coherent digital receiver, call-progress toner monitoring, 8-11 bit character lengths for asynchronous operation, and on-chip handshaking for the remote loopback test mode. Only connect and disconnect sequences are user-provided typically by a (generic) microcontroller.     

L波段集成自检源小型化多通道前端

L波段射频系统的前端模块,在完成放大滤波功能的基础上,还需要具有产生自检信号的功能,以及与上位机进行通信的能力。为了适应现代社会对设备功能完备、体积小、质量轻的要求,通过选用小型集成化跳频源,将数字控制、接口电路与微波控制电路相集成,将自检功分电路与微波控制电路集成,研制出一款集成自检源的多通道射频前端。在保证原有射频前端放大滤波功能、产生自检信号功能、与上位机进行通信功能的基础上,大幅度地减小了射频前端的体积与质量。通过实物制作与测试,验证了上述设计方法在保证多通道射频前端功能完整性的情况下可以大幅度减小整体模块的体积、减轻模块的质量。     

一种四通道PMC宽带数字接收机的设计与实现

介绍了一种通用宽带四通道数字接收机PMC背板的设计与实现.该设计用ADI公司的AD6645(14 bit,80 Msam-pie·s-1/105 Msample·s-1)作为模数转换器件,采用专用DDC芯片ISL5416和StratixⅡ系列的FPGA级联的结构,用PCI9656作为PCI接口芯片,板卡为标准PMC板型.文中给出了板卡的原理结构和性能指标的测试结果等.实践表明,该数字接收机具有精度高、使用灵活、处理和互联能力强等优点.     

A Unique Exciter and RF Subsystem for ABC'S Mobile Satellite News Gathering Terminal the ABSCamp System

ABC's mobile Satellite News Gathering (SNG) terminal consists of an antenna subsystem, RF subsystem, video exciter, and voice/data communications package. This paper describes the RF subsystem and video exciter. The SNG terminal is designed to provide the highest quality video transmission available in a mobile configuration. The exciter subsystem includes a new direct coupled (DC) modulator to optimize spectrum utilization and transmission quality. The RF subsystem features 300 watt traveling wave tube (TWT) amplifiers integral to the antenna feed support assembly which maximizes the power output capability of the SNG terminal. The RF subsystem also includes RF combining facilities required to simultaneously transmit both video and voice/data carriers, and RF switching facilities required to select between alternate polarizations and test modes. The RF subsystem incorporates built in test equipment useful for testing the SNG uplink prior to live transmissions, and includes monitor and control facilities which allow an operator in the SNG truck to operate the RF equipment mounted on the antenna. The RF subsystem is designed to allow configuration as a fully redundant terminal. However, the RF subsystem may be configured for non-redundant operation where the reduced system availability is justified by the cost savings.     

Over GHz low-power RF clock distribution for a multiprocessordigital system

Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution due to transmission line losses. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution,especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 μm TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node-board-level RF clock distribution networks is conducted using 3D full-wave EM simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers^Lt; RO3003 high-frequency organic substrate     

A method of surface clutter cancellation for an underground CWradar

An RF signal similar to the undesired signals is synthesized and used to cancel the undesired portion of the received signal from the antenna before it reaches the receiver. With a progressing degree of cancellation, the transmitter power is accordingly increased to expand the dynamic range of the radar. A canceller subsystem is proposed to eliminate undesired signals such as surface reflection and mutual coupling between antennas     

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of$-$110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates.     

基于GP2010的移动GPS射频前端设计

对GPS射频前端进行了研究与设计,实现了GPS信号射频到数字中频的转化过程。应用GP2010芯片设计出了符合要求的GPS射频前端,包括前端滤波器、低噪声放大器,以及中频滤波器。介绍测试系统的搭建,对实际制作的电路板进行调试,并得出测试结果,为后期基于FPGA实现GPS基带数字信号处理提供GPS数字中频信号,为自主设计GPS接收机奠定了基础。     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

面向IMT-Advanced的宽带OFDM-MIMO SDR平台

针对IMT-Advanced宽带通信系统的链路指标需求,提出了一款面向IMT-Advanced的宽带OFDM-MI-MO系统SDR平台,核心基板可提供单板2000万FPGA逻辑门的资源,汇聚1000M以太网,高速USB,高速嵌入式处理器,HSMC高速扩展接口.可实现对2G/3G/WLAN及未来的IMT-Advanced的系统通信链路的支持,通过灵活配置模拟射频前端载板,能实现对多种模式的MIMO支持,该平台具有硬件资源和互连资源丰富、工作频率高、性能稳定、扩展灵活等特点,可用于SDR平台搭建及宽带SOC芯片验证,基于该平台,已完成130Mbps OFDM-MIMO基带通信SOC的原型验证,表明其具有良好的实用价值.     

Built-in Self Test of RF Subsystems with Integrated Detectors

This paper describes a built-in self test technique for RF subsystems, using low-overhead on-chip detectors to calculate circuit specifications. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. The detector has small area overhead with a low-frequency output. A test chip was fabricated in a commercial 0.18 μm CMOS process. By using on-chip detectors in a loopback setup, both the system performance and specifications of the individual components can be accurately measured. Measurements show accurate prediction of system and component specifications.     

Code-width testing-based compact ADC BIST circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.