曙光1000A上消息传递与共享存储的比较

分布式共享存储虽然有易于编程的优点,但往往被认为效率不高、完全由软件实现的分布式共享存储系统（又称为虚拟共享存储系统）更是如此,文中以典型的消息传递系统ＰＶＭ与分布式共享存储系统ＪＩＡＪＩＡ粉列,报这两种并行程序设计环境的特点,并用７个应用程序在曙光１０００Ａ上分别比较了这两个系统的性能,实验３结果表明,ＪＩＡＪＩＡ的与ＰＶ玎当,但基于ＪＩＡＪＩＡ的并行程序设计却比ＰＶＮ简单得多。     

JAPS中通信支撑策略的比较

在分布式并行计算系统中,任务运行时支撑平台的功能和效率对并行执行的效果有着重要的影响,Ｊａｖａ言中的线程机制和ＲＭＩ机制为ＮＯＷ环境下的分布并行应用提供了高效的支持＾「１」。在基于Ｊａｖａ的自动并行编译系统ＪＡＰＳ＾「２」中,设计和实现了分别基于Ｊａｖａ ＲＭＩ和Ｓｏｃｋｅｔ通信支持策略的并行任务支撑平台ＰＴＳＰ;并比较了这两种通信策略对在ＮＯＷ环境下的分布式并行计算的支持能力和系统效率。     

COLLISION DETECTION AMONG MOVING OBJECTSIN MACHINING PROCESS SIMULATION

ＣＯＬＬＩＳＩＯＮＤＥＴＥＣＴＩＯＮＡＭＯＮＧＭＯＶＩＮＧＯＢＪＥＣＴＳＩＮＭＡＣＨＩＮＩＮＧＰＲＯＣＥＳＳＳＩＭＵＬＡＴＩＯＮＹａｎｇＨｅｍｉｎｇ；ＬｕＡｎｓｈｅｎｇ；ＺｈｏｕＪｉＣＯＬＬＩＳＩＯＮＤＥＴＥＣＴＩＯＮＡＭＯＮＧＭＯＶＩＮＧＯＢＪＥＣ...     

大众FA11主板推介

台湾大众电脑（ＦＩＣ）是著名的主板生产厂商之一,我想一些经常攒机的老鸟们一定不会陌生,最近该公司推出了基于ＶＩＡ Ａｐｏｌｌｏ Ｐｒｏ １３３Ａ ＶＩＡ芯片组,支持ＩＮＴＥＬ和 ＣＹＲＩＸ ＪＯＳＨＵＡ、 ＣＹＲＩＸＳＡＭＵＥＬ处理器的ＦＡ１１和ＦＡ３１主板。 大众ＦＡ１１主板采用ＶＩＡ ６９４Ｘ北桥和５９６Ｂ南桥芯片,ＡＴＸ结构。主板上面提供了三条ＤＩＭＭ插槽,最多支持达１．５ＧＢ的ＳＤＲＡＭ,当然也支持ＶＩＡ倡导的ＰＣ１３３标准。一条ＡＧＰ２Ｘ／４Ｘ插槽,五条ＰＣＩ以及一条ＩＳＡ插槽,提供了良好的全…     

油藏模拟线性解法包的并行实现

油藏模拟线性解法包的并行实现徐向明，孙家昶（中国科学院软件所并行软件研究开发中心）ＰＡＲＡＬＬＥＬＩＭＰＬＥＭＥＮＴＡＴＩＯＮＯＦＬＩＮＥＡＲＳＯＬＶＥＲＦＯＲＰＥＴＲＯＬＥＵＭＲＥＳＥＲＶＯＩＲＳＩＭＵＬＡＴＩＯＮ￥ＸｕＸｉａｎｇｍｉｎｇ；ＳｕｎＪ...     

简析VIA PRO266芯片组

ＶＩＡ ＰＲＯ２６６由北桥ＶＴ８６３３和南桥ＶＴ８２３３组成,支持ＳＯＣＫＥＴ３７０接口的 Ｉｎｔｅｌ Ｐｅｎｔｉｕｍ Ⅲ、Ｃｅｌｅｒｏｎ和 ＶＩＡ ＣｙｒｉｘⅢ系列。采用ＤＤＲ内存架构,ＦＳＢ速度为１３３ＭＨｚ,ＤＤＲ内存的运行速度就是２６６ＭＨｚ。内存带宽成倍的增加,峰值达到２．１ＧＢ／ｓ。最大支持２ＧＢ内存。并且,ＤＤＲ内存的工作电压是２．５Ｖ,可以有效的降低系统功耗。从系统上看,ＭＣＨ同时支持ＳＤＲＡＭ和ＤＤＲＲＡＭ,不排除有出现带有ＳＤＲＡＭ插槽的主板出现。 在北桥和南桥之间采用了Ｖ－ＩＪＮ…     

一种新的求解线性时变系统的数值解法

一种新的求解线性时变系统的数值解法贾磊，孙优贤（山东轻工业学院机电系）（浙江大学工业控制研究所）ＡＮＥＷＮＵＭＥＲＩＣＡＬＭＥＴＨＯＤＯＦＴＨＥＬＩＮＥＡＲＴＩＭＥ－ＶＡＲＩＮＧＳＹＳＴＥＭＳＶＩＡＳＨＩＦＴＥＤＪＡＣＯＢＩＳＥＲＩＥＳ￥ＪｉａＬｅｉ...     

YFSIM仿真软件交互子系统共享映象的生成

本文详细介绍了ＶＡＸ机上有ＶＭＳ操作系统支持下生成可共享映象的关键技术，并介绍了ＹＦＳＩＭ软件交互子系统部分共享映象的生成及使用过程中所遇到的一些问题和解决的办法。     

如何开发Java分布式应用程序

Ｊａｖａ ＲＭＩ实现了Ｊａｖａ同构环境下的分布式的对象计算。本文对Ｊａｖａ ＲＭＩ体系结构进行了探讨,分析了创建ＲＭＩ应用程序的方法和步骤,以及编译、发布和运行ＲＭＩ应用程序的具体过程。     

主板价格战激烈

华硕Ｓｏｃｋｅｔ Ａ系列主板平均降幅有１００元左右,降价后Ａ７Ｖ一Ｅ／ＫＴ１３３为８４０元,Ａ７Ｓ－ＶＭ／ＳＩＳ７３０Ｓ为７４０元,Ａ７ＶＩ－ＶＭ／ＫＭ１３３为７９０元, Ａ７ＶＬ—ＶＭ／ＫＬ１３３为６９０元。捷波推出了９９９元的ＫＴ２６６主板──Ｊ８６６ＡＳ。最新上市的精英Ｋ７ＡＭＡ主板采用黑色ＰＣＢ板,南北桥使用的是ＡＬＩ的芯片组,ＢＩＯＳ则是ＡＭＩ的,集成网卡;它上面只有４根ＰＣＩ槽;ＤＤＲ及ＳＤＲＡＭ插槽各有两根,售价８８０元。主板价格战激烈     

基于重排序变换和循环分布的通信优化算法

针对现有通信优化算法无法使MPI自动并行化编译器生成加速比理想的消息传递程序问题,提出了一种基于重排序变换和循环分布的通信优化算法。该算法根据给出的过程间副作用集合和基于mpi_wait/mpi_irecv移动的重排序变换规则,有序地采用重排序变换和循环分布,尽可能安全地扩大点到点非阻塞通信中通信与计算的重叠窗口,使MPI自动并行化编译器生成具有更多计算重叠通信的消息传递代码。实验结果表明,该算法能够隐藏更多的点到点非阻塞通信开销,并且明显提升消息传递程序的加速比。     

JAPS中的并行任务支撑平台PTSP

1 概述在现代计算技术中,分布并行处理越来越成为一种关键性的技术.这种由许多小任务合作解决大问题的方法,在过去几年发挥着越来越重要的作用,从高性能科学计算到日常事务的应用程序,都广泛接受和采纳分布并行处理,这是由于对高性能、低代价及强计算能力的需求所导致的,而大规模并行处理机(MPP)的     

JavaPIE：在Internet上延伸并行编程交互环境研究

ＪａｖａＰＩＥ是并行程序设计交互环境在Ｉｎｔｅｒｎｅｔ上的延伸,其设计目标是并行程序设计交互环境Ｐａｒａ－ＰＩＥ和自动并行化编译工程ＡＦＰ的底层支持,通过Ｊａｖａ实现的交互工具达到更理想的移植性、开放性和及共享性。它将并行化编译方法、程序语义分析技术、交互信息可视化工具、实验分析脚本文档有机地结合在一起,并在Ｉｎｔｅｒｎｅｔ上延伸出来,为蓬勃地开展并行程序设计交互环境的国际化合作研究开辟了广阔的前     

基于精确数组数据流分析框架的通信优化

为了提高消息传递型多处理器的性能,优化处理器间的通信对于并行化编译器至关重要。介绍了建立在精确数组数据流分析基础上的通信优化技术。通过优化,减少了通信次数,降低了通信代价。最后通过一个实例说明,在一定计算划分下结合精确数据流分析实现通信比仅仅依据计算划分实现通信能更有效地减少通信量。     

并行化编译中的一种集成优化方法

本文提出了一种面向分布存储器多机系统的并行化编译方法．针对分布存储并行系统的特点，作者采用的基本优化策略是：折衷并行性与数据引用局部性；减少和隐藏通信开销．通过对基于仿射函数的程序分解方式所导致的数据通信性质的分析，得到了适合分布存储结构特殊要求的并行性开发方法．为了在保持并行性的前提下最小化通信数据总量，提出了基于齐次线性方程组求解的程序全局优化分解方法．为了优化数据通信的组织，提高结点代码的效率，又提出了一种以线性不等式组作为工具的更加实用的通信优化和结点代码生成方法.     

A unified symbolic evaluation framework for parallelizing compilers

The quality of many optimizations and analyses of parallelizing compilers depends significantly on the ability to evaluate symbolic expressions and on the amount of information available about program variables at arbitrary program points. In this paper, we describe an effective and unified symbolic evaluation framework that statically determines the values of variables and symbolic expressions, assumptions about and constraints between variable values, and the condition under which control flow reaches a program statement. We introduce the program context, a novel representation for comprehensive and compact control and data flow analysis information. Program contexts are described as first order logic formulas, which allows us to use public domain software for standard symbolic manipulation. Computations are represented as algebraic expressions defined over a program's problem size. Our symbolic evaluation techniques comprise accurate modeling of assignment and input/output statements, branches, loops, recurrences, arrays, and procedures. All of our techniques target both linear, as well as nonlinear, expressions and constraints. Efficiency of symbolic evaluation is highly improved by aggressive simplification techniques. A variety of examples, including program verification, dependence analysis, array privatization, communication vectorization, and elimination of redundant communication, are used to illustrate the effectiveness of our approach. We present results from a preliminary implementation of our framework, which is used as part of a parallelizing compiler that demonstrates the potential performance gains achievable by employing symbolic evaluation to support program parallelization.     

An Object-Oriented Framework for Loop Parallelization

Generation of efficient parallel code is a major goal of a well-designed and developed parallelizing compiler. Another important goal is portability of both compiler system and the resulting output source codes. The various choices of current and future parallel computer architectures as well as the cost of developing a parallelizing compiler make portability a very important design goal. Since the design of parallelizing compilers is considerably move complex than designing conventional compilers, it is very important to achieve both efficiency and portability. To meet this dual goal, we have investigated the application of object oriented design to parallelizing compilers. Our parallelizing compiler design is based on abstractions of intermediate representations of loops and their class definitions. In this paper, we address the problem of loop parallelization and propose a framework where the loop parallelization process is divided into three phases and the optimization of loops is performed via a cyclic application of these three phases. The class of each phase is hierarchically derived from intermediate representations of loops. This facilitates the portability of the resulting parallelizing compilers. Furthermore, one of the phases uses a reservation table of hardware resources in order to obtain optimized parallel programs for given hardware resources. The validation of the proposed framework is given through the application of the object oriented design on an example program which is then parallelized efficiently.     

Grid平台上的NGS编译技术

随着网络技术的发展,在异构平台上使用共同的计算和信息资源将很快成为可能。Grid(网格)就是这样一种提供资源共享的新兴平台,而在其之上的下一代软件程序(NGS)则对编译器提出了新的挑战犤1犦。未来Grid平台上的编译系统将是能够进行动态编译和优化,根据实时系统以及网络的性能不断进行自我调整的软件模型,同时它还能为具有自适应性的应用程序提供编译支持。     

Efficient algorithms for data distribution on distributed memoryparallel computers

Data distribution has been one of the most important research topics in parallelizing compilers for distributed memory parallel computers. Good data distribution schema should consider both the computation load balance and the communication overhead. In this paper, we show that data redistribution is necessary for executing a sequence of Do-loops if the communication cost due to performing this sequence of Do-loops is larger than a threshold value. Based on this observation, we can prune the searching space and derive efficient dynamic programming algorithms for determining effective data distribution schema to execute a sequence of Do-loops with a general structure. Experimental studies on a 32-node nCUBE-2 computer are also presented