A 280 mW, 0.07% THD+N class-D audio amplifier using a frequency-domain quantizer

Pulse density modulation (PDM) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in pulse width modulation based amplifiers. However, their low-voltage analog implementations also require a linear loop filter and a quantizer. A PDM based class-D audio amplifier using a frequency-domain quantization is presented. The digital intensive frequency-domain approach achieves high linearity under low supply regimes. An analog comparator and a single-bit quantizer are replaced with a current controlled oscillator (ICO) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, single-bit, class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18???m CMOS process with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-?? loudspeaker load. The amplifier can deliver the output power of 280 mW.     

高效D类音频功率放大器的设计

D类功率放大器适应便携设备高效节能的客观需求,从而在音频模拟集成领域具有优势,随着设计技术的不断进步,D类功率放大器的性能指标也逐渐接近AB类放大器。通过分析基于CMOS工艺的D类音频功率放大器构成、驱动实现、性噪比、失真度等方面的特性来简要描述此类电路的设计思路。同时具体讨论了D类音频放大器各模块的工作原理和设计要点,针对设计要求比较高的驱动部分、抗干扰和噪声抑制部分以及抗EMS的设计都做了较详细的分析和论述。     

Carrier Distortion in Hysteretic Self-Oscillating Class-D Audio Power Amplifiers: Analysis and Optimization

An important distortion mechanism in hysteretic self-oscillating (SO) class-D (switch mode) power amplifiers-carrier distortion-is analyzed and an optimization method is proposed. This mechanism is an issue in any power amplifier application where a high degree of proportionality between input and output is required, such as in audio power amplifiers or xDSL drivers. From an average-mode point of view, carrier distortion is shown to be caused by nonlinear variation of the hysteretic comparator input average voltage with the output average voltage. This easily causes total harmonic distortion figures in excess of 0.1-0.2%, inadequate for high-quality audio applications. Carrier distortion is shown to be minimized when the feedback system is designed to provide a triangular carrier (sliding) signal at the input of a hysteretic comparator. The proposed optimization method is experimentally proven in an audio power amplifier leading to THD figures that are comparable to the state of the art. Experimental hardware is a hysteretic SO bandpass current-mode-controlled single-ended audio power amplifier capable of 45 W into 8 Omega or 80 W into 4Omega from a plusmn34 V supply with less than 0.03% THD from 100 Hz to 6.7 kHz. Carrier distortion is shown to account for this limitation in THD performance.     

A design methodology for high-order class-D audio amplifiers

This paper presents a design methodology for high-order class-D amplifiers, based on their similarity with sigma–delta ( $\Upsigma\Updelta$ ) modulators, for which established theory and toolboxes are available. The proposed methodology, which covers the entire design flow, from specifications to component sizing, is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high-end audio applications (THD  ≈ 90 dB), which would be unfeasible with conventional first-order class-D amplifiers.     

A CMOS low-distortion fully differential power amplifier withdouble nested Miller compensation

A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V_p-p differential output signal at 10 kHz and a load of 50 Ω. With an 8 Ω load and for a 10-kHz, 4-V _p-p output signal, THD is -68 dB. The chip area is 0.625 mm ² in a 1.5-μm single-poly, double-metal, n-well CMOS technology     

低失真正弦波逆变电源设计

D类功率放大器是一种相当成熟的宽频率功率低失真放大器件,直接用他构成当前大量使用的逆变电源核心电路,具有正弦波形失真低,电路结构简化,易于扩展设计等特点。使用现有技术成熟的成品器件有利于减少专用电源器件的开发和设计费用。通过对TDA7490的正弦逆变电源运用设计,尝试出一种利用D类开关音频器件设计低失真逆变电源的方法。     

用于数字D类放大器的双边PWM调制模块

文中介绍了一种双边PWM调制的数字D类放大器调制模块,使用伪自然采样法消除谐波失真。该伪采样算法是将牛顿-拉夫森迭代法和多项式逼近法相结合而形成的。近年来,虽有较多关于前沿PWM调制（LEPWM）和后沿PWM调制（TEPWM）的数字D类放大器的文献,但基于双边PWM（DEPWM）调制的数字 D类放大器方面的文献较少。因此本文利用现有的噪声整形技术,基于牛顿-拉夫森迭代法的伪采样算法等实现了一种用于数字D类放大器的双边PWM调制模块,并使用FPGA搭建了一个24位立体声数字音频D类放大器调制系统。经测试,该调制系统THD＋N@6 kHz性能达到-80.5 dB。     

Automatic topology selection and sizing of class-D loop-filters for minimizing distortion based on an evolutionary optimization kernel

This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated on two cases: for the design of a half-bridge amplifier and for a fully differential BTL class-D loop filter topology that achieves less than 0.003% THD at 680?mW output power in typical 0.18???m CMOS technology.     

A high efficiency PWM CMOS class-D audio power amplifier

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.     

Sliding mode audio class-D amplifier for portable devices

Audio class-D amplifiers are widely used in industrial and consumer portable electronic devices, such as mobile phones, thanks to their high efficiency. However, these amplifiers have a limited linearity due to their switching behavior and also a limited control bandwidth. To overcome these major drawbacks, this paper introduces a self-oscillating control technique based on the sliding mode theory which combines a large control bandwidth and a spread spectrum technique. A high power supply rejection, which is a crucial parameter in modules directly connected to a noisy battery, has also been achieved by introducing a variable hysteresis window. Theoretical analysis, behavioral and electrical simulations are discussed in detail in this paper. An integrated circuit using 0.13 μm CMOS process has been realized focused on mobile phone applications (0.8 W, 3.6 V and 8 Ω). The audio amplifier achieves 97 dB(A) signal-to-noise ratio, 0.02 % harmonic distortion and up to 80 dB of power supply rejection. The die area is smaller than 0.4 mm² while keeping more than 90 % efficiency at 1 W.     

Implementation of THD-reduction stereo audio amplifier using compensators and sigma–delta modulators

This paper presents an integrated stereo audio amplifier that employs sigma?Cdelta (????) modulation techniques with compensators. Traditional closed-loop audio amplifiers adopt pulse-width modulation or ???? modulation techniques. The design method proposed in this study uses a negative feedback closed-loop system with compensator and ???? modulator. This combination of compensator and ???? modulator significantly reduces the noise and total harmonic distortion (THD) compared with a traditional closed-loop system. The proposed negative feedback loop can automatically compensate for external perturbations, improving the precision of the eventual output. The compensator increases the audio-frequency loop gain, and leads to better rejection of audio-frequency disturbances. At a sample rate of 10?MHz, the proposed audio amplifier achieves 0.04% THD and a signal to noise ratio of 87?dB with efficiency above 92%. The proposed audio amplifier was implemented in a TSMC 3.3?V 0.35???m 2P4M CMOS process.     

D类音频功率放大器的研究与实现

介绍了采用D类放大器来完成音频信号变换与放大的电路设计。D类放大器采用了改进的方案,即用FPGA作为逻辑控制器实现对PWM H全桥功率放大电路的控制。设计的D类放大器可对数字音源输出的音频信号进行直接放大,为数字音源和功率放大的整合提供了完整的解决方案。他具有比其他类型放大器更高的效率和更低的转换失真,正越来越多地应用在便携式器件中,因此设计课题具有很好的现实意义。     

一种高效单相电源Ⅰ类线性音频功放的设计

采用SMIC0.18μm3.3V CMOS工艺,实现了单相电源Ⅰ类线性音频功放的设计。为了提高AB类功放的效率,设计了一种新型结构的Ⅰ类线性音频功放,并理论推导了它的效率。Ⅰ类音频放大器中的电源转换器能根据输入音频信号连续调节AB类功放的功率电源电压以减小功率管上的压降。为了使单相电源下PMOS和NMOS功率管功耗同时得到优化,设计了增益变化的信号处理电路。输出级采用桥式结构,并由三级运放构成以提高线性度。测试结果表明,该功放向8Ω阻性负载提供功率在小于270mW范围内时,总谐波失真与噪声之和小于0.45%,最大效率达到70%;功率在100mW范围内时,效率比AB类提高了一倍,且测试效率曲线与理论推导吻合。     

A 2.65 W high-fidelity filterless class D audio amplifier using multiple loop filters

The design of a 2.65 W, high-fidelity, filterless Class D audio amplifier in a standard 0.5 μm CMOS technology is proposed in this paper, where an architecture with multiple loop filters is utilized. This structure attenuates residual clock signals around the loop allowing very low total harmonic distortion (THD) and intermodulation distortion to be achieved in conjunction with high power supply rejection ratio (PSRR). The active area of this circuit is about 1.5 × 1.5 mm². The THD + N is <0.03 % at 1 kHz input frequency and 100 mW output power. The PSRR is ?80 dB at 217 Hz and maximum output power at 10 % THD is 2.658 W. A Figure of merit is defined to estimate the excellent performance which can meet the demands of portable communication devices greatly.     

A THD-reduction high-efficiency audio amplifier using inverter-based OTAs with filter-output feedback

This paper presents an integrated low-voltage THD-reduction high-efficiency class-D audio amplifier using inverter-based operational transconductance amplifiers (OTAs). We propose a negative feedback loop which can compensate for external perturbations and improving output precision. The compensator increases the audio-frequency loop gain, and leads to a better rejection of audio-frequency disturbances. The use of inverter-based OTA and comparator provides low-voltage operation and low-power dissipation. The audio amplifier operates with a 1.5 V supply voltage with maximum power efficiency of 90%. The proposed class-D amplifier was implemented using a TSMC 0.18-μm 1P6M CMOS process, and the active chip area is 1.87 mm².     

A power-efficient audio amplifier combining switching and lineartechniques

Integrated class-D audio amplifiers are very power efficient but require an external LC reconstruction filter, which prevents further integration. Also due to this filter, large feedback factors are hard to realize, so that the load influences the distortion and transfer characteristics. The 30 W amplifier presented in this paper consists of a switching part that contains a much simpler filter and a linear part that ensures a low distortion and flat frequency response. The switching part of the amplifier was integrated in a BCD process. Combined with a linear part and with a loudspeaker as load, it has a flat frequency response ±0.3 dB, a dissipation that is up to five times lower than a traditional class-AB audio amplifier, and a distortion of <0.02% over power and frequency range     

基于编码—解码模型的D类功率放大器行为建模

D类功率放大器具有优异的传输效率,属于开关类功放,其输出信号存在较大的非线性失真。对D类功率放大器进行行为建模时要同时考虑其非线性和记忆特性。文中将小波变换引入到编码—解码神经网络模型中,提出了小波编码—解码神经网络模型。使用基于门限循环单元的编码—解码模型和小波编码—解码模型进行D类功率放大器的行为建模。实验结果表明,文中提出的D类功率放大器行为模型相比于传统的Voterra-Laguerre模型而言,在信号的时域和频域都具有更高的精度。     

Boost bridge amplifier

A novel boost bridge amplifier which inherently doubles the power supply voltage, thus providing up to four times higher peak output power than a comparable state-of-the-art class-D amplifier, is proposed. The efficiency and the total harmonic distortion of both amplifiers during the amplification of a music signal are shown to be similar     

A new PWM controller with one-cycle response

This paper proposes a new nonlinear control technique that has one-cycle response, does not need a resetable integrator in the control path, and has nearly constant switching frequency. It obtains one-cycle response by forcing the error between the switched variable and the control reference to zero each cycle, while the on and off pulses of the controller are adjusted each cycle to ensure near constant switching frequency. The small switching frequency variation due to changes in the reference signal and supply voltage and delays in the circuit are quantified. Using double-edge modulation, the switching frequency variation is further reduced, thus, the associated signal distortion is minimized. An experimental 0-20 kHz bandwidth 95 W RMS power audio amplifier using the control method demonstrates the applicability of this control technique for high-fidelity audio applications. The amplifier has a power supply ripple rejection (PSRR) of 63 dB at 120 Hz. Additionally, the total harmonic distortion plus noise (THD+N) is less than 0.07% measured with a power supply ripple of 15%     

一种高效2.1声道D类音频功放设计

基于CSMC 0.5μm DPDM CMOS工艺,实现了一种具有2.1声道的D类音频功率放大器的设计,该功放由一个全桥差分输出结构的重低音功率放大器和两个半桥单端输出结构的立体声功率放大器构成。详细介绍了2.1声道D类音频功放的整体结构、前置运算放大器和轨至轨比较器的电路设计。仿真和测试结果表明:在电源电压5 V,该功放可向3Ω负载电阻提供2.5 W+0.6 W×2的输出功率;在电源电压3～6 V范围内,最大转换效率可达90%以上;重低音通道的总谐波失真与噪声之和小于0.7%,立体声通道的总谐波失真与噪声之和小于1%。