Ka-band analog front-end for software-defined direct conversion receiver

A six-port Ka-band front-end architecture based on direct conversion for a software-defined radio application is proposed in this paper. The direct conversion is accomplished using six-port technology. In order to demodulate various phase-shift-keying/quadrature-amplitude-modulation (PSK/QAM) modulated signals at a high bit rate, a new analog baseband circuit was specially designed according to the I/Q equations presented in the theoretical part. An experimental prototype has been fabricated and measured. Simulation and measurement results for binary PSK, quaternary PSK (QPSK), 8 PSK, 16 PSK, and 16 QAM modulated signals at a bit rate up to 40 Mb/s are presented to validate the proposed approach. A software-defined radio can be designed using the new front-end and only two analog-to-digital converters (ADCs) because the I/Q output signals are generated by analog means. Previous six-port receivers make use of four ADCs to read the six-port dc levels and require digital computations to generate the I/Q output signals. With the proposed approach, the load of the signal processor will therefore be reduced and the modulation speed can be significantly increased using the same digital signal processor.     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

A novel zero dead zone PFD and efficient CP for PLL applications

This paper presents a high dynamic range programmable gain amplifier (PGA) with linear-in-dB and digital to analog converter (DAC) gain control using a BiCMOS process. The proposed PGA is composed of a folded Gilbert variable gain amplifier cell, a DC offset cancellation circuitry, two inductorless fixed gain amplifiers with bandwidth extension, a symmetrical exponential voltage generator, a novel buffer amplifier with active inductive peaking for testing purposes and a 10 bit R-2R DAC. The linear-in-dB and DAC gain control scheme facilitate the analog baseband gain tuning accuracy and stability, which also provides an efficient way for digital baseband automatic gain control. The PGA chip is fabricated using 0.13 μm SiGe BiCMOS technology. With a power consumption of 80 mA@1.2 V supply voltage, the fabricated circuit exhibits a tunable gain range of ? 30–27 dB (DAC linear gain step guaranteed), a 3 dB bandwidth of around 3.5 GHz and a gain resolution of better than 0.07 dB.     

System simulations of a 1.5 V SiGe 81–86 GHz E-band transmitter

This paper presents simulation results for a sliding-IF SiGe E-band transmitter circuit for the 81–86 GHz E-band. The circuit was designed in a SiGe process with f _T  = 200 GHz and uses a supply of 1.5 V. The low supply voltage eliminates the need for a dedicated transmitter voltage regulator. The carrier generation is based on a 28 GHz quadrature voltage oscillator (QVCO). Upconversion to 84 GHz is performed by first mixing with the QVCO signals, converting the signal from baseband to 28 GHz, and then mixing it with the 56 GHz QVCO second harmonic, present at the emitter nodes of the QVCO core devices. The second mixer is connected to a three-stage power amplifier utilizing capacitive cross-coupling to increase the gain, providing a saturated output power of +14 dBm with a 1 dB output compression point of +11 dBm. E-band radio links using higher order modulation, e.g. 64 QAM, are sensitive to I/Q phase errors. The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices. The I/Q mismatch can be further reduced by adjusting varactors connected to each QVCO output. The analog performance of the transmitter is based on ADS Momentum models of all inductors and transformers, and layout parasitic extracted views of the active parts. For the simulations with a 16 QAM modulated baseband input signal, however, the Momentum models were replaced with lumped equivalent models to ease simulator convergence. Constellation diagrams and error vector magnitude (EVM) were calculated in MATLAB using data from transient simulations. The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed. For an average output power of 7.5 dBm, the design achieves 7.2% EVM for a 16 QAM signal with 1 GHz bandwidth. The current consumption of the transmitter, including the PA, equals 131 mA from a 1.5 V supply.     

A 2-V CMOS cellular transceiver front-end

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-μm CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-μm CMOS technology, without tuning or trimming     

一种基于MATLAB+正交上变频的模拟通信信号设计方法

文中提出了一种利用MATLAB 产生模拟通信信号的基带I/ Q 调制数据,通过FPGA+DAC 数字正交上变频来实现中频模拟通信信号产生的设计方法。该方法实现电路简单,不需要专门的模拟器件。通过该方法来实现模拟通信信号的产生,为构建更加复杂的电磁环境,实现雷达电子战和通信电子战领域的交织融合提供了有力保障,具有很强的实用价值。     

Interpolative Digital-to-Analog Converters

Interpolative digital-to-analog (D/A) converters produce a final output via a two-step process. First, each digital input word is used to control a circuit whose output oscillates rapidly (i.e., many times faster than new digital input values are provided) between coarsely spaced analog values (i.e., many times coarser than the resolution specified by the input word). Second, the oscillating analog signal is low-pass filtered to give the final output. The oscillation pattern is chosen to produce an average value that corresponds to the fine resolution specified by the input word and to ensure that the power of the error (the difference between the oscillating signal and the desired fine resolution output) occurs predominantly out of band. By this means, high-speed operation reduces the need for many finely spaced analog signal amplitudes, a tradeoff which is especially desirable for integrated circuit implementation. In this paper, the basic operation of interpolative D/A converters is described. Three alternative means of generating patterns are compared with respect to circuit complexity, and amount of baseband distortion introduced. The relative insensitivity of these converters to circuit value variations is emphasized. Applications of the interpolative technique to decoding digital words in both linear and piecewise linearly companded formats are given.     

A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter

A low-spurious low-power 12-bit 160-MS/s digital to analog converter (DAC) for baseband wireless transmitter is proposed and demonstrated. Degenerated current switches are introduced and benefits of using them are discussed. Mismatch behavior under packaging-induced die stress is also presented. The mobility shift caused by package stress inherited from a thin-die is a dominant source of I/Q mismatch. A 2-channel I/Q DAC core consumes 4 mA with a 1.3/2.6 V dual supply. The 0.13 mm² I/Q DAC core fabricated in 90-nm digital CMOS process with a highly-integrated digital processor achieves 74 dB SFDR, 55 dB SNDR, and -73 dB THD for a 975 kHz sinusoid at 153.6 MS/s sample rate     

Adaptive digital/RF predistortion using a nonuniform LUT indexing function with built-in dependence on the amplifier nonlinearity

This paper reports on an integrated adaptive digital/RF predistorter using a nonuniform spaced lookup table (LUT) and in-phase/quadrature (I/Q) RF vector multiplier (VM). The LUT contents are directly deduced from the baseband input and output signals of the power amplifier (PA). In addition, a new nonlinear indexing function of the predistortion LUT with built-in dependence on the PA nonlinearity is proposed. This function is made to be robust to the input signal statistics. A comparison of this new indexation method with conventional approaches, namely, power and logarithmic power indexation functions, is carried out. The superiority of the proposed scheme is demonstrated in particular for class-AB amplifiers where the gain of the PA varies over the whole input range of the drive signal. The measured output spectrum of a linearized 90-W peak lateral double-diffused metal-oxide-semiconductor PA reveals a significant reduction of the power emission at the adjacent channels of approximately 15 dB under IS95, single-carrier, and multicarrier wide-band code-division multiple-access signals. The experimental evaluation is carried out using an RF/digital predistorter prototype that mainly includes an envelope detector, a linear I/Q RF VM, field-programmable gate array and digital signal processor, and fast analog/digital and digital/analog converters.     

A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13 μm CMOS

A single-chip, dual-band transceiver for CDMA2000 is presented. The design supporting the North American cellular and PCS bands features a complete zero-IF receiver, a direct-conversion transmitter and two fully integrated synthesizers with VCOs. The analog receiver front-end comprises two self-matched wideband LNAs, a highly linear demodulator and a third-order baseband filter. In a test version I/Q ADCs and a digital front-end (DFE) to provide channel and matched filtering are included to demonstrate the performance of a fully integrated analog/digital line-up. Measured maximum SNR values of 23 dB and 25 dB for PCS and Cell bands, respectively, are achieved. The transmitter comprises baseband buffers and filters, an I/Q-modulator and separate output drivers for each band. An analog gain control (AGC) for realization of a dynamic range is implemented and a maximum output power of at a total CDG4 urban current of 34 mA is achieved for the PCS band. Measured ACPR1 and values are and 0.998 for the Cell band and and 0.995 for the PCS band, respectively. The chip is fabricated in a 0.13 RF-CMOS process, occupies a die size of 8.4 and operates with a 2.5 V supply.     

Mixed Cartesian feedback for Zero-IF WCDMA transmitter

In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA zero-intermediate frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback I/Q demodulator, and a digital stage adjusting the phase rotation around the loop. The whole system consumes 500 and 2.94 mW, respectively, for the analog and the digital part. System level simulation gave a maximum improvement of 35 dBc at 5 MHz from the carrier for the W-CDMA signal.     

Digital extraction of quantization error and its applications to successful design of sigma-delta modulator

A new technique to evaluate the quantization error of cascaded sigma-delta modulators in digital domain is presented. It avoids the complications associated with analog extraction of the quantization error in multistage noise shaping (MASH) modulators before feeding the error to the proceeding stage. Instead, the quantization error is estimated and cancelled out by adding a digital subtractor and by injecting a purely analog signal from the preceding stage to the next stage. In comparison to conventional MASH modulator structure, analog circuit requirements of the modulator are therefore relaxed, and the number of switched-capacitor digital-to-analog converters and the associated switching energy are lowered. In the absence of extra switching blocks, less flicker and thermal noise would be also injected into the circuit. Different implementations of MASH modulator are presented and analyzed based on the proposed digital quantization error extraction technique. Behavioral-level simulation results prove the mathematical equivalence of the proposed structures with successful MASH designs found in the literature, and confirm the effectiveness of the idea. For a ? 1.4 dB, 19.8 kHz input and an oversampling ratio of 16, a modified 1-V 20-MS/s 2 + 2 MASH modulator achieves a signal-to-noise-and-distortion ratio (SNDR) of 78 dB, when the input of the first quantizer is fed to the second stage. The second design based on digital extraction of quantization error achieves a 71 dB SNDR for a ? 8.0 dB, 19.8 kHz input, when the second stage is fed by the output of the first integrator.     

A 53mW IQ pipelined ADC for WLAN front end

This paper presents an analog to digital converter (ADC) architecture suitable for wideband wireless receiver system. The in-phase (I) and quadrature (Q) ADCs work independently, but share on-chip reference buffer and non-overlapped clock generation block for balance between two channels. The single ADC core consists of one front sample and hold amplifier, four cascade of 2.5 bit pipeline stages with pseudo-class AB opamp shared between adjacent stages and one 2 bit backend flash stage. The prototype was fabricated in standard 130 nm CMOS process and occupied silicon area of 0.62 mm². Performance of 66 dB spurious-free-dynamic-range is measured at 80 MS/s with 1 Vpp input signal. The power dissipation of the whole chip is only 53 mW from a 1.1 V supply.     

A Complex Image Rejection Circuit With Sign Detection Only

In direct-conversion receivers, radio frequency (RF) signals are down-converted to low or zero intermediate frequency (IF) using complex in-phase and quadrature (I/Q) mixers with no prior image filtering. Due to I/Q path gain and phase errors, image leaks into the signal band during the down-conversion process. A generic image rejection algorithm is proposed to reject image in the baseband using a zero-forcing sign-sign adaptive feedback concept. The orthonormal property of complex I/Q channels is exploited to update their gain and phase errors by detecting only four signs, and image is corrected with four multiplications and two additions. The proposed image rejection algorithm can be implemented in a digital, analog, or hybrid form. A complex baseband sample and hold (S/H) with a digital error detector, which is a hybrid example, achieves an image rejection of 65 dB while sampling at 40 MS/s. The prototype chip fabricated in 0.18-mum CMOS occupies 800times450 mum², and consumes 23 mW at 1.8 V     

Improved digital-IF transmitter architecture for highly integrated W-CDMA mobile terminals

An improved digital intermediate frequency (IF) transmitter architecture for wide-band code-division multiple-access (W-CDMA) mobile terminals is proposed. Based on the heterodyne design but without requiring any off-chip IF filter, the transmitter enjoys the advantages of a homodyne architecture (such as circuit simplicity, low power consumption, and a high level of integration) while avoiding the performance problems associated with direct upconversion. By implementing the quadrature modulation in the digital domain and requiring only a single path of analog baseband circuits, inherently perfect I/Q matching and good error vector magnitude (EVM) performance can be achieved. The IF is chosen to be a quarter of the clock rate for a very simple and low-power digital modulator design. The difficulties of on-chip IF filtering were greatly alleviated by 1) performing a careful frequency planning and 2) employing a special-purpose digital-to-analog converter to produce high-order sin(x)/x rolloff. System-level simulation demonstrates that spurious-emission requirements are met with virtually no dedicated reconstruction filter circuits. This architecture takes full advantage of complimentary metal-oxide-semiconductor technology scaling by employing digital processing to ease analog complexities.     

A combined low power SAR capacitance-to-digital analog-to-digital converter for multisensory system

A combined successive approximation (SAR) capacitance-to-digital converter (CDC)/analog-to-digital converter (ADC) for biomedical multisensory system is presented in this paper. The two converters have same circuit blocks and can be exchanged by four switches. Capacitance or voltage from different sensing elements can be measured and converted to digital output directly. This single chip takes place of separated CDC and ADC so that the power consumption of the multisensory system is reduced. The asynchronous SAR circuit has low power and small area. A dynamic comparator with zero-static power is adopted. Switches are carefully designed to reduce the non-idealities of the converter. Several techniques, such as bootstrapped switches, bottom-plate sampling, dummy switches are used to improve the performance of the circuit. The CDC/ADC is fabricated in 0.18 μm CMOS process. Measurement results show that the ENOB of this 11 bits converter is 10.15 bits and its FOM is 45 fJ/conversion-step under 200 kHz sampling. The power consumption is 9.4 μW with 1.4 V power supply voltage and the core area is 0.1764 mm².     

Mixed-signal quadrature demodulator with a multicarrierregeneration system

This paper presents a combined analog/digital demodulation system built around a (PLL) with digital carrier regeneration. The input signal itself is not digitized, but the PLL is digital wherever it is possible. The link between the analog and the digital domain is a 1-bit sigma-delta converter that converts the (quasi-dc) output signal of the PLL's phase detector into a bitstream. The PLL's loop filter doubles as a decimation filter for the bitstream. The analog I and Q output signals are obtained by multiplying the analog input signal with the digital output signal of the PLL in two four-quadrant multiplying digital-to-analog converters     

A cost-effective three axis CMOS accelerometer combining micromachining and digital technology

In this paper, a three axis accelerometer is successfully developed by a mixing-mode chip design using CMOS surface-micromachining technology. The chip consists of mass-spring, the analog core and the digital circuit. The vibration sensor is implemented with micro-spring to change the capacitance between two metals. The analog core detects the capacitance differential to the frequency shifting using an oscillator. The digital control is to compute the amount of acceleration to the form of digital bit. The chip can detect the acceleration to 140 g for x axis and y axis with 10-bit resolution, and from 110 g for z axis with 9 bits. The detected speed is about 4 k bits per second, for three-axis output in parallel. The chip size is about 1,400 × 1,400 um², when TSMC 0.18 um 1P6 M process is employed. This 3D accelerometer can directly connect to the digital interface with three serial-port output for the information of X, Y and Z axis.     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

L, C and X band integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to digital converter (ADC) for a synthetic aperture radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm². The RF front end consists of three parallel signal channel intended for L, C and X-band of the SAR receiver. The BB is selectable between 50 and 160 MHz bandwidths through switches. The ADC has selectable modes of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 and 37 dB and noise figure of 11 and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz BB and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz BB and 8 bit mode ADC.