至强走单骑——英特尔首次在单路服务器中引入至强处理器

2006年9月7日,英特尔发布了面向入门级服务器市场的双核至强3000系列处理器和与之配套的3000／3010芯片组。此次产品发布首次将中高端服务器处理器品牌——至强(Xeon)引入到入门级的服务器产品中。     

全新英特尔至强7300系列处理器的平台

本刊9月6日讯:全新英特尔(?)至强(?)多路7300系列服务器平台(Caneland)。由全新四核英特尔(?)至强7300系列处理器(Tigerton)和具备数据流量优化(Data Traffic Optirnizations)特性的英特尔7300芯片组(研发代号"Clarksboro")构建而成。     

虚拟化应用的最佳平台 英特尔全新高端至强7400服务器处理器

9月22日,英特尔在京发布7款45nm英特尔至强7400系列处理器产品。全面提升性能标尺,并为虚拟化性能表现设定了全新标准。     

双核至强处理器面世——英特尔发运多核服务器平台

随着计算机处理器的速度不断刷新的同时，芯片的能耗也在不断提高。如何解决二者的矛盾，促使芯片生产厂商把更多的目光转向了“多内核”芯片产品。     

英特尔的“世界波”——全新双核英特尔至强5100系列处理器平台发布侧记

有专家把“双核英特尔至强处理器5100系列”的面市,视为全球IT业世界杯中,最精彩的一记“世界波”。     

英特尔至强7500处理器

本刊讯3月31日,英特尔推出升级为Nehalem架构的至强7500系列处理器,该产品可用于构建从双路到最高256路的服务器系统,与已被广泛采用的上一代产品至强7400相比,其性能平均提升达3倍之多,从而在企业级性能基准测试中创下了更为领先的成绩。     

虚拟照进现实——英特尔至强7400系列服务器平台发布

2008年9月22日。英特尔与众多合作伙伴共同在北京发布全新英特尔至强7400系列服务器平台。这也标志着英特尔多路服务器处理器全面进入了45纳米时代。至强7400系列处理器可在一个处理器芯片上最多提供6个处理核心以及16MB共享缓存．为企业数据中心提供了出色的扩展性和可靠性．充足的计算线程．丰富的内存资源。同时．7400系列处理器凭借增强的虚拟化性能以及英特尔虚拟化技术（VT）FlexMigration,     

更快的服务器CPU——英特尔至强7400系列处理器

随着互联网应用的发展以及云计算的异军突起,企业级服务器对计算速度及功耗的要求也越来越高,强大的数据处理能力、复杂的数据库处理能力、繁重的科学数据计算以及各种庞大的网络服务需求都对服务器处理器的芯片技术提出了更高的要求。2007年9月,英特尔推出了至强7300系列服务器处理器芯片,推动了4核处理器的发展和应用。时隔一年,2008年9月22日,英特尔在北京发布了7款45纳米英特尔至强7400系列处理器产品,     

打造高效通信网络 英特尔至强处理器E5-2600

日前,全新的英特尔至强处理器E5-2600产品家族与Intel Data PlaneDevelopment Kit(Intel DPDK)一起登场,它们将能够支持电信设备制造商将三种通信工作负载整合到单一的英特尔架构平台之上。这一能力使服务提供     

英特尔发布32纳米制程的至强5600系列处理器

2010年3月17日,本刊讯,英特尔公司在北京发布了新一代智能服务器处理器——英特尔至强处理器5600系列。据了解,该系列处理器传承了英特尔创新的智能计算理念,主要用于     

基于Intel Xeon Phi的激光等离子体粒子模拟研究

激光等离子体粒子模拟广泛用于探索极端物质状态下的科学问题。将一种基于粒子云网格方法的三维等离子体粒子模拟程序LARED P移植到Intel Xeon Phi协处理器上。在移植的过程中,综合运用了Native和Offload两种编程模式：首先运用Native模式对LARED P程序中热点计算任务进行优化研究,通过采用SIMD扩展指令使该计算任务获得了4.61倍的加速;然后运用Offload模式将程序移植到CPU-Intel Xeon Phi异构系统上,并通过使用异步数据传输和双缓冲技术分别提升了程序性能9.8%和21.8%。     

Benchmarking Performance of a Hybrid Intel Xeon/Xeon Phi System for Parallel Computation of Similarity Measures Between Large Vectors

The paper deals with parallelization of computing similarity measures between large vectors. Such computations are important components within many applications and consequently are of high importance. Rather than focusing on optimization of the algorithm itself, assuming specific measures, the paper assumes a general scheme for finding similarity measures for all pairs of vectors and investigates optimizations for scalability in a hybrid Intel Xeon/Xeon Phi system. Hybrid systems including multicore CPUs and many-core compute devices such as Intel Xeon Phi allow parallelization of such computations using vectorization but require proper load balancing and optimization techniques. The proposed implementation uses C/OpenMP with the offload mode to Xeon Phi cards. Several results are presented: execution times for various partitioning parameters such as batch sizes of vectors being compared, impact of dynamic adjustment of batch size, overlapping computations and communication. Execution times for comparison of all pairs of vectors are presented as well as those for which similarity measures account for a predefined threshold. The latter makes load balancing more difficult and is used as a benchmark for the proposed optimizations. Results are presented for the native mode on an Intel Xeon Phi, CPU only and the CPU \(+\) offload mode for a hybrid system with 2 Intel Xeons with 20 physical cores and 40 logical processors and 2 Intel Xeon Phis with a total of 120 physical cores and 480 logical processors.     

Performance benchmarking of deep learning framework on Intel Xeon Phi

The Journal of Supercomputing - With the success of deep learning (DL) methods in diverse application domains, several deep learning software frameworks have been proposed to facilitate the usage...     

ETA: experience with an Intel Xeon processor as a packet processing engine

Server-based networks have well-documented performance limitations. These limitations outline a major goal of Intel's embedded transport acceleration (ETA) project, the ability to deliver high-performance server communication and I/O over standard Ethernet and transmission control protocol/Internet protocol (TCP/IP) networks. By developing this capability, Intel hopes to take advantage of the large knowledge base and ubiquity of these standard technologies. With the advent of 10 gigabit Ethernet, these standards promise to provide the bandwidth required of the most demanding server applications. We use the term packet processing engine (PPE) as a generic term for the computing and memory resources necessary for communication-centric processing. Such PPEs have certain desirable attributes; the ETA project focuses on developing PPEs with such attributes, which include scalability, extensibility, and programmability. General-purpose processors, such as the Intel Xeon in our prototype, are extensible and programmable by definition. Our results show that software partitioning can significantly increase the overall communication performance of a standard multiprocessor server. Specifically, partitioning the packet processing onto a dedicated set of compute resources allows for optimizations that are otherwise impossible when time sharing the same compute resources with the operating system and applications.     

Improvement of workload balancing using parallel loop self-scheduling on Intel Xeon Phi

In recent years, Intel promotes its new product Xeon Phi coprocessor, which is similar to the x86 architecture coprocessor. It has about 60 cores and can be regarded as a single computing node, with the computing power that cannot be ignored. This work aims to improve the workload balance by parallel loop self-scheduling scheme performed on Xeon Phi-based computer cluster. The proposed concept is implemented by hybrid MPI and OpenMP parallel programming in C language. Since parallel loop self-scheduling composes of static and dynamic allocation, weighting algorithm is adopted in the static part, while the well-known loop self-scheduling is adopted in dynamic part. The loop block is partitioned according to the weighting of MIC and HOST nodes. Accordingly, Xeon Phi with many-core is adopted to implement parallel loop self-scheduling. Finally, we test the performance in the experiments by four applicable problems: matrix multiplication, sparse matrix multiplication, Mandelbrot set and circuit meet. The experimental results indicate how to do the weight allocation and which scheduling method can achieve the best performance.     

英特尔中文盒装处理器更新包装

为了帮助IT部门更好地评估和保护诸如桌面、笔记薄、智能电话、MP3播放器和拇指驱动器之类的网络端点设备的安全，Novell近日宣布了其危险评估调查的初始结果，显示表明许多企业仍极易受到伤害一些可预防的安全威胁。到目前为止，该调查揭示出许多重大漏洞，     

High-performance simulations of turbulent boundary layer flow using Intel Xeon Phi many-core processors

The Journal of Supercomputing - Direct numerical simulations (DNS) of turbulent flows have increasing importance because they not only provide fundamental understanding of turbulent flows but also...     

柯尼卡美能达黑白激打印系列全新上市

正结实耐用,方便快捷是大多数用户对于入门级打印产品的主要需求。近日柯尼卡美能达推出多款黑白激光打印机、一体机,为用户们提供更多的办公选择。其中,pagepro 1500W/1550DN单功能黑白打印机可以能满足基本打印需求,而对于希望整合办公资源精打细算的用户,即将在10月底上市的pagepro1580MF/1590MF黑白多功能一体机也是不可多体(仅富     

Improving performance of iterative solvers with the AXC format using the Intel Xeon Phi

The Journal of Supercomputing - This work is focused on the application of the new AXC format in iterative algorithms on the Intel Xeon Phi coprocessor to solve linear systems by accelerating the...     

丽讯将发布全新D5系列投影机

随着家用需求的日益增长,投影机已经成为家庭影音娱乐的核心设备。对于SOHO一族及上班族来说,一台兼具工作、娱乐功能的投影机无疑是首选。为了满足消费者兼顾商用和家用投影的需求,丽讯中国即将发布一系列小巧高亮、功能强大的投影机新品——D5系列。该系列产品多达10款左右,将全部采用最新的德州仪器DMD芯片。