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1.
<正>3瞬态电流谱和瞬态电阻谱中两种电子气的动态电流峰为了深入研究器件射频工作中的电流崩塌,许多作者测量了栅漏偏置电压改变时沟道的动态输运行为,获得了大量瞬态电流谱和瞬态电阻谱。大家认为这些电流谱和电阻谱都是陷阱俘获电子耗尽沟道二维电子气造成的。因此文献中都先加一个脉冲来给器件中的陷阱充电,让陷阱俘获电荷后耗尽沟  相似文献   

2.
光激发半导体硅片对宽带太赫兹波的调制研究   总被引:3,自引:3,他引:0  
利用光泵浦-太赫兹(THz)探测(OPTP)技术,研究 了THz波在Si半导体界面间的传输行为。通过改变抽 运光密度从而改变样品表面的载流子浓度,实现对THz波透射/反射的有效调制。在外加中心 波长为800nm 的飞秒激光激发块体半导体Si片时,成功实现了对宽带THz波时域谱包括入射THz 脉冲振幅和 相位以及THz波次级反射峰抗反射的调制。光激发Si片可以获得任意载流子浓度 的Si片实现对 THz脉冲振幅的调制,调制度达到90%以上;光激发Si片能够使THz脉 冲的相位发生负延迟,随着 泵浦光密度的增加,负的相移越来越明显,随着频率的增高,负的相移也越来越明显;光激 发Si片还能够 对THz波的次级反射峰进行调制,随着泵浦光密度的改变,实现对次级反射峰的π相位以及 次级反 射峰抗反射的调制。光激发Si片对宽带THz波时域谱的调制为THz波在通信、国防安全等领域 的应用奠定了基础。  相似文献   

3.
比较了GaN体材料和GaN HFET中陷阱的不同行为,发现后一种陷阱不能简单地用陷阱中心俘获带内电子模型来解释,由此建立起描述沟道电流的新局域电子气模型。运用这一局域电子气新概念解释了实验中观察到的各类瞬态电流谱,说明目前瞬态电流研究把高密度局域电子气误认为"陷阱"而引入的各种误解。提出了通过能带剪裁来解决GaN HFET电流崩塌和可靠性难题的新途径。  相似文献   

4.
研究了CaxSr1-xS;Eu,Sm(x=O~1)的光激励发光和吸收性质,测量了样品的红外光激励谱。发现激发后样品在红外区的吸收增强,增强部分的波长分布与光激励谱相同,峰的位置随组分x值而变化,同时在这些谱带上还发现了一些次级结构。由此说明Sm^3 对陷阱的红外激励吸收的影响。据此提出一个复合陷阱模型,指出电子俘获中心并非Sm^3 附近形成的晶格缺陷。  相似文献   

5.
用深能级瞬态谱(DLTS)研究了分子束外延生长的高纯GaAs薄膜中的深能级.带金电极的高纯GaAs薄膜经不同温度的热退火,其DLTS峰谱的位置和幅度均发生变化.这是由于在热退火中金电极与GaAs反应,从而出现各种各样的DLTS峰谱.来用器件制造的台面腐蚀工艺去除反应物后的DLTS峰谱退化为一个单峰谱.本文结合伏安特性的测量结果对DLTS峰谱的变化进行了分析和讨论.  相似文献   

6.
应用direct-current current voltage(DCIV)和电荷泵(change pumping)技术研究了LDD nMOST's在热电子应力下产生的界面陷阱.测试和分析的结果显示,一股额外的漏端电流影响了DCIV谱峰中表征漏区的D峰.这股电流主要是陷阱辅助隧穿电流.  相似文献   

7.
多陷阱相干效应对氧化层电流弛豫谱的影响   总被引:1,自引:0,他引:1  
本文用单陷阱产生一俘获模型和一级电场因子近似弛豫函数研究了“多陷阱相干效应”对簿栅氧化层电流弛豫谱(OCRS)的影响。给出了高场下、多陷阱共存时,各陷阱OCRS峰并存的条件和峰位、峰值的修正公式。  相似文献   

8.
张金风  郝跃 《半导体学报》2006,27(2):276-282
观察了AlGaN/GaN HEMT器件在短期应力后不同栅偏置下的一组漏极电流瞬态,发现瞬态的时间常数随栅偏压变化很小,据此判断这组瞬态由电子陷阱的释放引起.为了验证这个判断,采用数值仿真手段计算了上述瞬态.分别考虑了在器件中不同空间位置的电子陷阱,分析了应力和瞬态中相应的陷阱行为,对比和解释了仿真曲线与测量结果的异同.基于上述讨论,提出测量的瞬态可能是表面深陷阱和GaN层体陷阱的综合作用的结果.  相似文献   

9.
观察了AlGaN/GaN HEMT器件在短期应力后不同栅偏置下的一组漏极电流瞬态,发现瞬态的时间常数随栅偏压变化很小,据此判断这组瞬态由电子陷阱的释放引起.为了验证这个判断,采用数值仿真手段计算了上述瞬态.分别考虑了在器件中不同空间位置的电子陷阱,分析了应力和瞬态中相应的陷阱行为,对比和解释了仿真曲线与测量结果的异同.基于上述讨论,提出测量的瞬态可能是表面深陷阱和GaN层体陷阱的综合作用的结果.  相似文献   

10.
用光激瞬态电流谱(OTCS)方法测量半绝缘InP:Fe的深能级,研究了光强对OTCS测试的影响,在低温下,用强光滑蜊测得InP:Fe中存在ET=0.34eV的电子陷阱和ET=1.13eV的空穴陷阱,光强增大,ET=0.34eV的电子陷阱的OTCS峰的位置向高温方向移动,不同的光强下测得的ET也不同。文章从光的强度影响深能级的填充率对ET进行了理论修正。实验上发现修正后误差大大减小了。  相似文献   

11.
Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.<>  相似文献   

12.
In this paper a number of deep traps, which play a crucial role in many macroscopic properties of semi-insulating GaAs have been characterized and analyzed. The main trap parameters (activation energy and capture cross section) were deduced by several experimental methods, based on thermally stimulated current and isothermal current transients. Results were compared with other studies of deep traps in SI GaAs performed with these and other methods as well as studies of deep levels in conductive GaAs. To enable these comparisons an analysis of the methods and usually employed calculation procedures was given as well as suggestions for the presentation of the trap parameters. It was also concluded that the observed traps are complex defects which correspond to deep traps observed by other authors in a variety of other SI GaAs materials. Some of them seem to include, as a part of the defect, a well known defect EL2 but there are also strong indications for involvement of other structural defects and/or common impurities.  相似文献   

13.
This work demonstrates that the "purity", meaning the low density of electron traps in a semi-insulating (SI) SiC substrate, can be crucial for the electrical characteristics of 4H-SiC MESFETs. Structures realized on two types of SI substrates have been investigated. The first kind is vanadium doped substrates grown by the classical Physical Vapor Transport (PVT) sublimation technique. The second kind are extremely low vanadium content SI substrates grown by the high temperature CVD (HTCVD) technique. For all the transistors, I/sub d/-V/sub ds/ measurements have been performed as a function of temperature. Different parasitic effects have been observed on the static output characteristics in the case of PVT substrates. Frequency dispersion measurements of the transconductance and drain-source output conductance, have next been realized. The results give clear evidence of the presence of deep traps in the transistors realized on PVT substrates. Those traps have an activation energy of 1.05 eV and a capture cross section between 10/sup -18/ cm/sup -2/ and 10/sup -19/ cm/sup -2/. They are most probably related to vanadium. The correlation between the presence of these traps and the parasitic effects on the output characteristics is discussed and the trap localization in the structure is established. In the case of HTCVD very low vanadium substrates, no parasitic effect have been observed and the presence of traps was not detected by the different characterization techniques.  相似文献   

14.
The role of contacts in characterization of traps in semi-insulating (SI) GaAs by thermally stimulated current (TSC) methods has been demonstrated by comparing alloyed In and soldered In contacts. Alloyed In contacts, which have an ohmic characteristic, assure high sensitivities in both TSC and temperature dependent photocurrent (PC), and both are important for determining the trap concentrations in SI GaAs. On the other hand, soldered In contacts, which act like Schottky barriers, cause a significant reduction of both PC and TSC, particularly at low temperatures, and can lead to a misinterpretation of TSC results.  相似文献   

15.
Deep centers in undoped semi-insulating InP   总被引:1,自引:0,他引:1  
Undoped semi-insulating (SI) InP samples, subjected to one-step and multi-step wafer annealing, and lightly and normally Fe-doped SI InP samples without annealing have been characterized by thermally stimulated current (TSC) spectroscopy. A dominant deep center at 0.63 eV is found in all samples and is undoubtedly due to iron. Two prominent TSC traps, Tb (0.44 eV) and Td (0.33 eV), found in undoped SI InP, are thought to be related to the phosphorus antisite PIn, and traps at low temperatures, like Te* (0.19 eV), to the phosphrus vacancy VP.  相似文献   

16.
Numerical simulation of sidegating effect in GaAs MESFET's   总被引:3,自引:0,他引:3  
Two-dimensional simulation of the sidegating effect in GaAs MESFETs has been performed. The result confirms that Schottky contacts on a semi-insulating substrate cause serious high substrate leakage current and drain current reduction in GaAs MESFETs. The threshold behavior in the sidegating effect is found to correlate with the conduction behavior of the Schottky-i-n (sidegate) structure when the sidegate is negatively biased. Shielding and enhancement of the sidegating effect by the Schottky contacts have also been studied, and the results agree with the experimental findings. Besides, the presence of hole traps in the semi-insulating substrate is found to be essential to the sidegating effect  相似文献   

17.
对液封直拉(LEC)非掺磷化铟(InP)进行930℃ 80h的退火可重复制备直径为50和75mm的半绝缘 (SI)衬底.退火是在密封的石英管内纯磷(PP)或磷化铁(IP)两种气氛下进行的.测试结果表明IP-SI InP衬底具有很好的电学性质和均匀性,而PP-SI的均匀性和电学参数都很差.在IP-SI样品的PL谱中出现与深缺陷有关的荧光峰.光激电流谱的测量结果表明:在IP气氛下退火获得的半绝缘磷化铟中的缺陷明显比PP-SI磷化铟的要少.并对退火后磷化铟中形成缺陷的机理进行了探讨.  相似文献   

18.
对液封直拉(LEC)非掺磷化铟(InP)进行930℃ 80h的退火可重复制备直径为50和75mm的半绝缘 (SI)衬底.退火是在密封的石英管内纯磷(PP)或磷化铁(IP)两种气氛下进行的.测试结果表明IP-SI InP衬底具有很好的电学性质和均匀性,而PP-SI的均匀性和电学参数都很差.在IP-SI样品的PL谱中出现与深缺陷有关的荧光峰.光激电流谱的测量结果表明:在IP气氛下退火获得的半绝缘磷化铟中的缺陷明显比PP-SI磷化铟的要少.并对退火后磷化铟中形成缺陷的机理进行了探讨.  相似文献   

19.
在室温条件下 ,研究了辐照偏置、总剂量和剂量率对 PMOS剂量计辐照剂量记录 -阈电压的稳定性影响 ,观察了辐照后阈电压在不同栅偏条件下的变化趋势和幅度。分析认为慢界面陷阱中电荷的“充放电”是造成不稳定的首要原因。结果表明 ,该种由慢界面态造成的阈电压变化在每次开机测量下具有重复性。讨论了在 PMOS剂量计中提高稳定性的办法。  相似文献   

20.
We have subjected n-channel power VDMOSFETs to a positive and negative high electric field stress (HEFS) followed by biased annealing at 150 °C. Stress-induced defects have been monitored using midgap-subthreshold and charge-pumping techniques, the use of which in tandem has enabled an insight into behaviours of fixed and switching traps in the gate oxide and oxide/silicon interface. The repetition of the stress/annealing sequence has resulted in some quantitative but no qualitative differences in response compared to the original sequence. We have observed complex kinetics of different types the stress-induced defects during post-HEFS annealing, including an intriguing latent buildup of “true” interface traps. Comparison of post-HEFS and post-irradiation annealing data has indicated differences of the nature of defects induced by Fowler-Nordheim injection and irradiation in our samples.  相似文献   

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