基于伪随机的微处理器验证方法及改进

处理器验证是验证工作中最重要也是时间开销最大的部分.文中提出了一种基于仿真的微处理器验证方法,以伪随机算法为主自动生成测试向量,实现了验证的自动化和验证环境的可重用性.并在此基础上引入神经网络算法,提高了整个验证过程的自动化程度和效率.通过一款DSP处理器的验证结果表明,该方法确实提高了微处理器功能验证的有效性和完备性.     

A static verification approach for architectural integration of mixed-signal integrated circuits

In this paper we present a static method for verifying the proper integration of analog and mixed-signal macroblocks into an integrated circuit. We consider the problem in a setting where there is no golden reference for verifying the validity of the interconnections between the blocks. The proposed verification methodology relies on an abstract modeling of the functional behavior of the blocks and a set of consistency criteria defined over the composition of these abstract models. A new formalism called mode sequence chart (MSeqC) has been presented for capturing the behavior of the blocks at a level of abstraction that is suitable for interconnection verification. We present rules to compose the MSeqCs of each block in an integrated design and present three criteria that indicate possible interconnection faults. We present a tool called AMS-IV (AMS-interconnection verification) that takes the design netlist as input, the MSeqC model of each design block as reference, and tests the three criteria.     

基于VMM的L2 Cache的验证平台的设计与实现

随着集成电路行业的不断发展,芯片设计规模空前增长,功能也越来越复杂,使得验证的难度和重要性日益增大。在此提出一种由System Verilog语言搭建的基于VMM的一种面向对象的验证平台。该验证平台主要使用覆盖率驱动的验证技术,并结合可约束随机测试和记分板技术,对一款多核处理器芯片中的L2 Cache进行功能验证。最后对验证平台的可重用性进行研究。实验结果表明,验证平台具有良好的激励生成机制,能够对L2 Cache模块的功能进行全面的验证;同时,验证平台经过少量更改就可以在基于标准的AXI接口的So C验证平台之间重用,极大地提高了验证效率,缩短了验证时间。     

一种激光标刻图像验证装置的研究与设计

为了解决激光打标控制卡在开发制作过程中标刻图像验证困难的问题,设计了一种激光标刻图像验证装置。该装置首先是通过主控模块FPGA来控制串口线进行激光打标卡的数据采集,然后经过数据检测、判别和存储后筛选出振镜坐标数据和激光器开关光数据,通过USB总线将数据传输至PC上位机,最终由上位机还原数据实现图像的模拟标刻,该装置的数据采集遵循XY2-100协议,FPGA主控模块选用Cyclone III芯片,USB传输模块选用FT2232H芯片。该装置能够快速、完整的获取激光打标控制卡在进行图像标刻过程中的实时数据,并能在上位机模拟绘制出实际标刻的图案。实验结果表明,该硬件装置运行稳定、精度较高、图案验证性强。     

Formal verification of analog and mixed signal designs: A survey

Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.     

降低系统芯片中跨时钟域设计和验证复杂度的方法

在系统芯片设计中,直接采用现有的跨时钟域信号处理方法不仅设计复杂度高而且验证难度大.为了解决这个问题,将跨时钟域设计与功能设计完全分离,在每个通信接口部件中采用独立的、专用的跨时钟域处理模块统一解决跨时钟域信号的传输问题,并通过封装点对点通信接口和合并处理同一方向的跨时钟域信号,将需要处理的跨时钟域信号的数量减少为方向相反的2组.实验结果表明,该方法能够有效降低跨时钟域设计的验证难度和系统芯片的设计复杂度,并且不会明显增加功能部件的传输延迟和面积开销.     

基于物联网技术的智能家电管理模型设计与验证

随着科学技术的飞速发展和生活水平的逐步提升,人们对家电产品的效率及质量也提出了更高的要求。物联网这一现代化技术的发展和运用,有效解决了这一问题,其在加快智能家电发展进程的基础上,大大促进了人们生活形态的改变。本文以基于物联网技术的智能家电管理模型为研究课题,首先介绍各种物联网的核心技术,其次深入分析了智能家电管理的设计与验证,从而为今后的此领域的开发研究者提供有效的参考。     

基于物联网技术的智能家电管理模型设计与验证

随着科学技术的飞速发展和生活水平的逐步提升,人们对家电产品的效率及质量也提出了更高的要求。物联网这一现代化技术的发展和运用,有效解决了这一问题,其在加快智能家电发展进程的基础上,大大促进了人们生活形态的改变。本文以基于物联网技术的智能家电管理模型为研究课题,首先介绍各种物联网的核心技术,其次深入分析了智能家电管理的设计与验证,从而为今后的此领域的开发研究者提供有效的参考。     

网络支付协议的形式化安全需求及验证逻辑

从整个网络支付协议的安全角度出发，提出网络支付协议的多层安全需求模型，包括以认证和密钥分配为基础的基层需求、网络支付协议固有的中层需求(包括保密性、原子性、公平性、完整性、匿名性、不可否认性、可追究性等)、以及面向具体应用的高层需求。基于一阶逻辑和时序逻辑，提出一种适合描述网络支付协议的形式化安全需求的逻辑，描述了该逻辑的语法结构和推理规则，并用该安全需求逻辑对网络支付协议的多层安全需求进行了形式化描述。最后，以SET协议为例进行需求验证。     

A model-based and simulation-driven methodology for design of haptic devices

High precision and reliable haptic devices are highly complex products. The complexity that has to be carefully treated in the design process is largely due to the multi-criteria and conflicting character of the functional and performance requirements. These requirements include high stiffness, large workspace, high manipulability, small inertia, low friction, high transparency, as well as cost constraints. The requirements are a basis for creating and assessing design concepts. Concept evaluation relies to a large extent on a systematic usage of kinematic, dynamic, stiffness, friction, and control models. The design process can benefit from a model-based and simulation-driven approach, where one starts from an abstract top-level model that is extended via stepwise refinements and design space exploration into a detailed and integrated systems model that can be physically realized. Such an approach is presented, put in context of the V-model, and evaluated through a test case where a haptic device, based on a Stewart platform, is designed and realized. It can be concluded, based on simulation and experimental results that the performance of this deterministically optimized haptic device satisfies the stated user requirements. Experiences from this case indicate that the methodology is capable of supporting effective and efficient development of high performing haptic devices. However, more test cases are needed to further validate the presented methodology.     

基于FPGA的DDR2 SDRAM接口信号完整性设计与验证

对高速DDR2 SDRAM接口信号进行完整性仿真分析,并根据仿真结果得到相应PCB设计规则,最终通过使用FPGA实现了对大容量DDR2 SDRAM的读写控制,板卡验证测试,达到了预期的效果。     

Modelling,simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioural VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.     

A design methodology for low-leakage and high-performance buffer based on deviant behavior of gate leakage

Based on the observation that both subthreshold and gate leakage depend on transistors width, this paper introduces a feasible method to fast estimate leakage current in buffers. In simulating of leakage current with swept transistor width, we found that gate leakage is not always a linear function of the device geometry. Subsequently, this paper presented the theoretical analysis and ex- perimental evidence of this exceptional gate leakage behavior and developed a design methodology to devise a low-leakage and high-performance buffer with no penalty in area using this deviation.     

A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level

In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely affect circuit reliability. It becomes therefore imperative to develop reliability-aware design tools to mitigate their impact on circuits. To this end, these phenomena must be first accurately characterized and modeled. And, since all these phenomena reveal a stochastic nature for deeply-scaled integration technologies, they must be characterized massively on devices to extract the probability distribution functions associated to their characteristic parameters. In this work, a complete methodology to characterize these phenomena experimentally, and then extract the necessary parameters to construct a Time-Dependent Variability model, is presented. This model can be used by a reliability simulator.     

A unified look at the use of successive differentiation and integration in MOSFET model parameter extraction

This article provides a unified look at MOSFET model parameter extraction methods that rely on the application of successive differential and integral operators, their ratios, and various other combinations thereof. Some of the most representative extraction procedures are assessed by comparatively examining their ability to extract basic model parameters from synthetic MOSFET transfer characteristics, generated by an ad hoc minimalist four-parameter model. The model used, comprised of a single polylogarithm function of gate voltage, approximately describes in a very concise manner the essential features of MOSFET drain current continuously from depletion to strong inversion. The exponential-like low voltage and monomial-like high voltage asymptotes of this simple model are conveniently used to analyze and compare the different extraction schemes that are founded on successive differentiation or integration. In addition to providing a combined view useful for comparative methodological appraisal, the present unified analysis facilitates visualizing and exploring other potentially promising extraction strategies beyond the straightforward use of successive differential and integral operators and their ratios. We include examples of parameter extraction from measured transfer characteristics of real experimental MOSFETs to comparatively illustrate the actual numerical implementation of typical successive differential and integral operator-based procedures.     

Railway satellite channel at Ku band and above: Composite dynamic modeling for the design of fade mitigation techniques

Past studies on the railway satellite channel (RSC) at Ku band and above consider exclusively the attenuation coming from the metal power arches (PAs) along the railway route, producing significant though deterministic periodical fast fading. Nevertheless, limited attention has been given to model tropospheric effects on the RSC. The present paper takes a more comprehensive view of the RSC by introducing a novel stochastic dynamic model of rain fading in mobile satellite systems on top of the diffraction because of PAs. The proposed approach builds upon well‐established research on rain attenuation time series synthesizers employing stochastic differential equations. It is shown that this propagation tool may provide significant aid, in general, in mobile satellite system simulations and in the design of fade mitigation techniques (FMTs), particularly aiming at the railway scenario. The tool enables the generation of fade events, fade duration statistics, rain attenuation power spectrum and predicting the necessary FMT control loop margin. This is particularly useful for the RSC because most of the proposed FMTs focusing on PAs are not appropriate for compensating atmospheric fading. Copyright © 2011 John Wiley & Sons, Ltd.     

A density functional study of structural,electronic and optical properties of titanium dioxide: Characterization of rutile,anatase and brookite polymorphs

Study of fundamental physical properties of titanium dioxide (TiO₂) is crucial to determine its potential for different applications, such as study of electronic band gap energy is essential to exploit it for optoelectronics and solar cell technology. We present here investigations pertaining to structural, electronic and optical properties of rutile, anatase and brookite polymorphs of TiO₂ by employing state of the art full potential (FP) linearized (L) augmented plane wave plus local orbitals (APW+lo) approach realized in WIEN2k package and framed within density functional theory (DFT). To incorporate exchange correlation(XC) energy functional/potential part into total energy, these calculations were carried out at the level of PW–LDA, PBE–GGA, WC–GGA, EV–GGA, and mBJ–GGA which are exploited as the manipulated variables in this work. From our computations, the obtained structural parameters results were found to be consistent with the available experimental results. The analysis of electronic band gap structure calculations point to TiO₂ as a semiconducting material in all three phases, whereas band gap character around Fermi level was found to be indirect for anatase, and direct for rutile and brookite phases. Density of state (DOS) profiles showed a substantial degree of hybridation between O 2p and Ti 3d in conduction and valence band regions, illustrating a strong interaction between Ti and O atoms in TiO₂ compund. In addition, our investigations of the optical properties also endorse the interband transitions from O 2p in valence band to Ti 3d in conduction band.