A Manufacturing Process for Analog and Digital Gallium Arsenide Integrated Circuits

A process for manufacturing small-to-medium scale GaAs integrated circuits is described. Integrated FET's, diodes, resistors, thin-film capacitors, and inductors are used for monolithic integration of digital and analog circuits. Direct implantation of Si into >10/sup 5/ omega/spl dot/cm resistivity substrates produces n-layers with +-10-percent sheet resistance variation. A planar fabrication process featuring retained anneal cap (SiO/sub 2/), proton isolation, recessed Mo-Au gates, silicon nitride passivation, and a dual-level metal system with polyimide intermetal dielectric is described. Automated on-wafer testing at frequencies up to 4 GHz is introduced, and a calculator-controlled frequency domain test system described. Circuit yields for six different circuit designs are reported, and process defect densities are inferred.     

An electron beam activated switch and associated memory

A new type of electron beam activated switch (EBAS) is described which utilizes electron beam induced charge storage in the metal-oxide-semiconductor (MOS) system. The state of the EBAS is determined by monitoring the surface conductance of the semiconductor. After discussing the basic charge-storage phenomena, memory arrays that use the electron beam for storing and reading information are described. A matrix array of EBASs in which information is stored using the electron beam and read by row-column access circuits is discussed in detail. The time to store a bit of information is a function of the current density of the electron beam; an approximate dosage of 10^-5C/cm²is required for storage. A memory design using Schlesinger's microspot tube for the electron optics is discussed. It is shown that storage of 1.0 × 10⁷bits per tube should be possible with presently available electron optical design and semiconductor technology.     

Fabrication of high-performance AlxGa1-xAs/InyGa1-yAs/GaAs resonant tunneling diodes using amicrowave-compatible technology

A microwave-compatible process for fabricating planar integrated resonant tunneling diodes (RTDs) is described. High-performance RTDs have been fabricated using Al_xGa_1-xAs/In_y Ga_1-yAs/GaAs strained layers. Peak-to-valley current ratios (PVRs) of 4.8:1 with simultaneous peak current densities of 4×10⁴ A/cm² have been achieved at room temperature for diodes of area 9 μm². Accurate measurements of reflection gain versus frequency between 1.5 and 26.5 GHz in the negative differential region indicate that the present technology is promising for millimeter-wave integrated circuits including self-oscillating mixers, frequency multipliers, and detectors     

Issue logic for a 600-MHz out-of-order execution microprocessor

The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm² in a 0.35-μm CMOS process     

The minimization of parasitics in integrated circuits by dielectric isolation

A radically new technique for the fabrication of integrated circuits which completely changes microelectronic design is described. In place of the back-biased pn junctions usually used for isolation of devices in a substrate, a dielectric is substituted whose properties are such that almost total isolation is achieved with no increase in area. Leakage currents are reduced by several orders of magnitude to around 10^-10amperes/cm², stray capacitances to around 10^-5pf/µ², parasitic npnp and pnpn action is eliminated, and breakdown voltage is increased up to 1000 volts. Great flexibility in the design of components is achieved through the ability to place highly conductive "wells" where needed to obtain the benefits of epitaxial techniques, and by the ability to use devices having higher breakdown voltages. The technique makes practically all circuit configurations possible, and greatly enhances the possibilities for fabrication of npn and pnp transistors in the same substrate. Some details on circuits fabricated by this technique are given, such as digital circuits with propagation delay times of 3 nanoseconds and a video amplifier with a gain-bandwidth product of over 700 Mc.     

Hybrid IRCCD imaging array

A hybrid IRCCD for high background application has been successfully fabricated. The device consists of fifty Hg0.7Cd0.3Te detector diodes of 50-µm × 50-µm sensitive areas and a silicon CCD maltiplexer with input circuits on 40-µm centers having bucket background subtraction and blooming protection circuits. The noise-equivalent power (NEP) of the IRCCD is 5 × 10^-14W-Hz^-1/2at background photon flux level of 4 × 10¹⁵photons . cm^-2s^-1, integration time of 2 × 10^-5s, and clock frequency of 3 × 10⁶Hz. The noise source of the detector diodes limits the IRCCD performance. The IRCCD is also evaluated with the real-time raster-scanned thermal images displayed on a CRT monitor. Two-dimensional images are generated by using a scanning mirror. A fixed-pattern noise is reduced by comparison of an object video to the reference video stored in a memory. A noise-equivalent temperature difference of the system is 0.6°C at a frame rate of 30 Hz. Instantaneous field of view is 1 mrad × 1 mrad and the field of view of the system is 12° × 5.7°.     

Effective Pigtailing Method for Fiber Arrays to InP-Based Photonic Integrated Circuits

A reliable technology for interfacing signals in both the optical and electrical domain that provides the possibility of precise control of the thermal optical chip properties is an essential requirement to utilize photonic integrated circuits in system-related areas. Hence, a practical assembly method is developed here to connect fiber arrays to a wide range of different kinds of advanced Indium Phosphide-based photonic integrated circuits. The essence of this procedure is a well-controlled step-by-step pigtailing approach whereby any misalignments during the assembly process can be compensated for using laser supported adjustment. The pigtailing process of two different multiport photonic integrated circuits is described. The circuits include an integrated two-state multiwavelength laser chip, operating at 25 $^{circ}$C, and a coupled Mach–Zehnder interferometer chip, operating at 10 $^{circ}$ C. Both devices function as a 1 bit optical memory element with optical set and reset functions. Successful alignment compensation on the order of 0.1 ${-}3 mu$m is demonstrated. Subsequently, the subassemblies are fixed unambiguously on thermo-electric coolers in a package with a clamp method to reduce internal stress in the subassembly. Consequently, the mechanical alignment stability of both devices are proven to be smaller than 25 nm/ $^{circ}$C, as measured in a temperature range from 10 $^{circ}$C to 30 $^{circ}$C.      

A BiCMOS process utilizing selective epitaxy for analog/digitalapplications

A 2-μm BiCMOS process that has been designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar with an f_T of 3.0 GHz, and a nonoptimized vertical p-n-p structure into a 2-μm CMOS process with poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps, and with no changes to the critical process parameters that determine the performance of the MOS transistors. The circuit worthiness of the process is demonstrated by fabricating CMOS, vertical n-p-n RTL, and vertical p-n-p RTL ring oscillators, and demonstrating high yields for these circuits     

Normal-incidence, high-temperature, mid-infrared, InAs-GaAsvertical quantum-dot infrared photodetector

The growth, fabrication, and characterization of a normal-incidence, high-temperature, mid-wavelength infrared, InAs-GaAs vertical quantum-dot infrared photodetector with a single Al_0.3 Ga_0.7As current-blocking barrier are described and discussed in detail. A specific detectivity ≈3×10⁹ cmHz^1/2/W is measured for a detector temperature of 100 K at a bias of 0.2 V. Detector characteristics are measured for temperatures as high as 150 K. The superior low bias performance of the vertical quantum-dot infrared photodetector ensures its compatibility with commercially available silicon read-out circuits necessary for the fabrication of a focal plane array     

Quantum flux parametron: a single quantum flux device for Josephsonsupercomputer

A quantum flux parametron (QFP), a single quantum flux superconductive device that has a potential of up to 100-GHz switching with nW-order power dissipation, is considered. The potential of the QFP and key technologies when QFPs are applied to a Josephson supercomputer are described. Switching speed, stability, and power dissipation of a QFP are discussed. QFP gates, circuits, and systems are next described. Then, ultra-fast clock distribution using a standing wave is explained. High-speed operation at more than 10 GHz and 10¹⁴ error-free operations per QFP have been demonstrated. Finally described is a high-density packaging scheme by three-dimensional integration, which is very important for ultra-high speed circuits because the propagation delay becomes dominant in such circuits     

Scaling I2L for VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I²L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I²L devices with geometries >1 µm is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I²L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted.     

A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting the circuits in a way which is difficult to design for, making calibration an attractive solution. Both the calibration algorithm and test chip implementation are described and measured results are presented. The CDR circuit was fabricated in a 0.18-mum, six metal layer standard CMOS process. With a pseudorandom bit sequence of 2⁷ - 1 calibration improved the measured bit error rate from 4.6 x 10^-2 to less than 10^-13.     

An insect vision-based motion detection chip

The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-μm CMOS process and occupies an area of 2×2 mm²     

A process for the combined fabrication of ion sensors and CMOScircuits

A novel process for the fabrication of ion-selective field-effect transistors (ISFETs) together with CMOS circuits on the same chip is reported. The process is based on a standard 2-μm, n-well, CMOS process, which is only modified starting at the metal interconnect step. The interconnect layer used is tungsten silicide. ISFETs are fabricated with floating polysilicon gates, which are exposed to photolithographic masking and HF etching before silicon nitride is deposited on the wafer. This layer of Si₃N₄ acts both as the pH-sensitive insulator for the ISFETs and as a protection layer for the on-chip circuitry buried beneath it. A source-follower circuit is described that provides an output voltage dependent on the threshold-voltage variations of the sensing transistor     

A new MOS integrated circuit fabrication using Si3N4film self-alignment liftoff techniques

A new MOS integrated circuits fabrication process that realizes self-aligned source and drain contact hole formation is described. This process utilizes a Si3N4film self-alignment liftoff technique for selective oxidation (SALTS). Devices are fabricated using SALTS. It is shown that device packing density and speed show a 30-percent or more improvement over the conventional method at the same minimum lithographic feature size. It is also shown that Si3N4film deposited using the sputtering method does not cause any degradation in device characteristics.     

A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuitin 1.2-μm CMOS

A parallel architecture for high-data-rate AGC/decision/clock-recovery circuit, recovering digital NRZ data in optical-fiber receivers, is described. Improvement over traditional architecture in throughput is achieved through the use of parallel signal paths. An experimental prototype, fabricated in a 1.2-μm double-poly double-metal n-well CMOS process, achieves a maximum bit rate of 480 Mb/s. The chip contains variable gain amplifiers, clock recovery, and demultiplexing circuits. It yields a BER of 10^-11 with an 18 mV_p-p differential input signal. The power consumption is 900 mW from a single 5 V supply     

NMOS IC's for clock and data regeneration in gigabit-per-secondoptical-fiber receivers

The design and performance of two essential analog circuits in optical-fiber receivers is described. A time-interleaved decision circuit is capable of regenerating 35-mV nonreturn-to-zero (NRZ) data inputs to full logic levels at 1.1 Gb/s with 10^-11 bit error rate (BER), and a phase-locked loop (PLL) extracts the clock from a 2 ²³ long pseudorandom sequence at 1.5 Gb/s with 13-ps r.m.s. jitter. The two circuits have been implemented as 1-μm NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively     

The CW optically pumped 12.08µm Raman laser theory and experiments for high power-conversion efficiency

A model is developed to predict the performance of the continuous-wave CO2-pnmped 12.08 μm NH3laser which is operated by a two-photon or Raman-like process. The local gain and pump absorption are determined from a two-wave three-level treatment based on the density matrix formalism. A ring cavity configuration is considered and interaction of the two intensities inside the cavity are described using coupled wave equations. The subsequent 12.08μm output intensity is calculated for a wide range of operational parameters (injected pump intensity, NH3gas pressure, pump frequency offset, gain length, output coupling,... ). For a well optimized system, power-conversion efficiencies of 10-30 percent should be realistically obtained by pumping with a conventional CW CO2laser. Experiments illustrating the major conclusions are described.     

Fabrication of ECL gate arrays on quick turn-around line

A quick turn-around line (QTL) technology, including a high-speed on-line data system, electron-beam direct writing, and dry process technologies are described in this paper. Electron-beam pattern data is converted by a VAX 11/780 and transmitted to the electron-beam exposure system (EBES) through a communication controller at the speeds of 1 Mbits/s. After various data manipulations, patterns are quickly written directly on wafers. The first metal layer using an Al-Si-Cu alloy is etched in a reactive ion beam etcher with carbon tetrachloride (CCl4). In order to avoid the charge-up phenomenon of the electron beam, the surface of the silicon nitride (SiN) interlevel insulation layer is coated with a thin conductive layer of TiW. TiW/SiN layers are successively etched by the reactive ion etching (RIE) with CF4+ O2(2%). The damage induced by electron-beam irradiation on the device is perfectly annealed out with a 450°C anneal. Bias-temperature tests have been performed on various logic circuits used in a main frame computer.     

A 10-b 20-Msample/s analog-to-digital converter

A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm² and dissipates 240 mW