A rotary encoder based on magneto-optical storage

A new kind of the rotary encoder based on the magneto-optical (MO) storage is proposed. Using the MO methods, a small high-precision high-response rotary encoder can be realized. High precision is achieved by a two-stage process in which the code disk is firstly written using the direct transfer recording, and then rewritten using the corrections based on the measured errors. The systems for writing to, reading from, and evaluating the MO encoder are developed, with the optimal MO encoder reading and writing parameters determined experimentally. A trial MO encoder with a resolution of 9000 pulses/revolutions is created directly from a reference encoder, delivering an accuracy of approximately 2.8 in. The maximum resolution and response frequencies achieved are 18000 p/r and 400 kHz. After the corrected transfer recording, accuracies of 1.3 in at a resolution of 2250 p/r and 1.7 in at 9000 p/r are achieved.     

正余弦编码器细分技术研究

为提高正余弦编码器的分辨率,提出用硬件细分的方法将512刻线的正余弦编码器进行信号12倍频,利用比较器和异或门搭建电路,将输出信号倍频12倍,该方法读数迅速,能达到动态测量的要求,而且成本低。详细分析其工作原理,用Saber软件进行电路仿真。仿真结果表明该方法能使512p/r分辨率的编码器提高到6 144p/r,在实际应用中得到了验证。     

An integrated per-channel PCM encoder based on interpolation

Describes a novel technique called interpolation which has been used to integrate a per channel PCM encoder in a standard digital circuit technology. This encoder converts voiceband analog signals to both an oversampled 1-bit code and uniform PCM with /spl mu/-law companding noise. The circuit comprises approximately 550 integrated injection logic gates together with a resistive digital-to-analog converter, a voltage reference, and a simple differential amplifier. The encoder is part of a full PCM codec chip set suitable for a broad range of voiceband telecommunication applications.     

Adaptive statistical encoding of d.p.c.m.-coded videotelephone signals

Adaptive statistical encoding of d.p.c.m.-coded video-telephone signals is considered. The need for an adaptive statistical encoder to operate on short-term batch statistics is explained and the effect on the bit rate of limiting the number of codes employed by the statistical encoder is reported.     

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

The hardware implementation of the intra prediction described in this paper allows the H.264/AVC encoder to achieve optimal compression efficiency in real-time conditions. The architecture has some features that distinguish it from other solutions described in literature. Firstly, the architecture supports all intra prediction modes defined in High Profile of the H.264/AVC standard for all chroma formats. Secondly, the architecture can generate predictions for several quantization parameters. Thirdly, the hardware cost is reduced as the same resources are used to compute prediction samples for all the modes. Fourthly, the high sample-generation rate enables the encoder to achieve high throughputs. Fifthly, 4?×?4 block reordering and interleaving with other modes minimize the impact of the long-delay reconstruction loop on the encoder throughput. The architecture is verified against the JM.12 reference model and within the real-time FPGA hardware encoder. The synthesis results show that the design can operate at 100 MHz and 200 MHz for FPGA Aria II and 0.13 μm TSMC technology, respectively. These frequencies allow the encoder to support 720p and 1080p video at 30 fps.     

Convolutional codes over integer rings suitable for parallel and serial concatenation

Choosing a convolutional encoder over a ring with feedback may not lead to a suitable component code for parallel or serial concatenation. A simple criterion is derived that allows to check whether a rational encoding matrix generating some convolutional code over the integer ring /spl Zopf/(p/sup m/) ( p prime) has exclusively infinite impulse responses.     

Rotational invariance of trellis codes. II. Group codes anddecoders

For pt.I see ibid., vol.42, no.3, p.751-65 (1996). In Part I, general results on rotationally invariant codes and encoders were derived assuming no algebraic structure. In Part II, trellis codes based on group systems are considered as a special case for which code and encoder constructions are particularly simple. Rotational invariance is expressed as an algebraic constraint on a group code, and algebraic constructions are found for both “absorbed precoder” encoders and for encoders with separate differential precoders. Finally, the various encoder forms used to achieve rotational invariance are compared based on their performance on an AWGN channel     

Improvements to delta-sigma modulators when used for p.c.m. encoding

The letter describes some improvements to a delta-sigma modulator when it is used as part of a p.c.m. encoder for telephony applications. These improvements reduce the clock-rate requirements of the modulator, which would otherwise be excessive, and also minimise problems introduced by the use of low-precision components.     

Art of constructing low-complexity encoders/decoders forconstrained block codes

A rate p : q block encoder is a dataword-to-codeword assignment from 2^p p-bit datawords to 2^p q-bit codewords, and the corresponding block decoder is the inverse of the encoder. When designing block encoders/decoders for constrained systems, often, more than 2^p codewords are available. In this paper, as our main contribution, we propose efficient heuristic computer algorithms to eliminate the excess codewords and to construct low hardware complexity block encoders/decoders. For (0,4/4) and (0,3/6) PRML constraints, block encoders/decoders generated using the proposed algorithms are comparable in complexity to human-generated encoders/decoders, but are significantly simpler than lexicographical encoders/decoders     

Rate k/(k+1) punctured convolutional encoders

G.D. Forney (1970, 1975) defined a minimal encoder as a polynomial matrix G such that G generates the code and G has the least constraint length among all generators for the code. Any convolutional code can be generated by a minimal encoder. High-rate k(k+1) punctured convolutional codes were introduced to simplify Viterbi decoding. An ordinary convolutional encoder G can be obtained from any punctured encoder. A punctured encoder is minimal if the corresponding ordinary encoder G is minimal and the punctured and ordinary encoders have the same constraint length. It is shown that any rate k/(k+1), noncatastrophic, antipodal punctured encoder is a minimal encoder.<>     

An analysis on optimal rates of BDB encoders for RLL and MTR systems

In most recording channels, modulation codes are employed to transform user data to sequences that satisfy some desirable constraint. Run-length-limited (RLL(d,k)) and maximum transition run (MTR(j,k)) systems are examples of constraints that improve timing and detection performance. A modulation encoder typically takes the form of a finite-state machine. Alternatively, a look-ahead encoder can be used instead of a finite-state encoder to reduce complexity. Its encoding process involves a delay called look-ahead. If the input labeling of a look-ahead encoder allows block decodability, the encoder is called a bounded-delay-encodable block-decodable (BDB) encoder. These classes of encoders can be viewed as generalizations of the well-known deterministic and block-decodable encoders. Other related classes are finite-anticipation and sliding-block decodable encoders. In this paper, we clarify the relationship among these encoders. We also discuss the characterization of look-ahead and BDB encoders using the concept of path-classes. To minimize encoder complexity, look-ahead is desired to be small. We show that for nonreturn to zero inverted (NRZI) versions of RLL|,(0,k),RLL(1,k), and RLL(d,infin), a BDB encoder does not yield a higher rate than an optimal block-decodable encoder. However, for RLL(d,k) such that dges4 and d+2lesk相似文献   

Pitch synchronous differential predictive encoding system

A pitch synchronous differential predictive encoding system (p.s.d.p.e.) is described, which reduces the dynamic range of voiced speech to a value similar to that of unvoiced speech. As a consequence, the signal encoded has a smaller dynamic range than the speech signal and results in an improvement in the signal/noise ratio for a given transmitted number of bits per sample. This improvement is approximately 8 dB compared with an a.d.p.c.m. codec, when the p.s.d.p.e. system uses an adaptive p.c.m. encoder and the transmission rate is 3 bit/sample.     

一种新的脉动阵列RS码编码方法

本文首先讨论了一种适用于高速场合的RS编码器的算法与结构－它由r 1个脉冲单元组成,其中r为校验位的数目。这种编码算法是基于码生成元矩阵的栖西表达,编码器中没有限制其开关速度的全局时钟,故可在高速场合中得到应用,然后给出了一种应用于该编码器的改进方案：该方案消除了栖西单元中的除法器,并且还没有了求逆运算,故降低了编码器的复杂度,可有效地加速编器的数据吞吐率,从而使其更适用于极高速场合。     

A 212 MPixels/s 4096 $times$ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications

Multiview video coding (MVC) plays an important role in a 3-D video system. In addition, the resolution of HDTV is increasing to present more vivid perception for users. To realize real-time processing of dozens of TOPS, VLSI solution is necessary. However, ultra high computational complexity, a large amount of external memory bandwidth and on-chip SRAM size, and complex MVC prediction structures are three main design challenges of implementation of MVC hardware architecture. In this paper, an MVC single-chip encoder is proposed for H.264/AVC Multiview High Profile and High Profile for 3-D and quad full high definition (QFHD) TV applications, respectively. The 4096 × 2160 p multiview video encoder chip is implemented on a 11.46 mm² die with 90 nm CMOS technology. An eight-stage macroblock pipelined architecture with proposed system scheduling and cache-based prediction core supports real-time processing from one-view 4096 × 2160 p to seven-view 720 p videos. The 212 Mpixels/s throughput is 3.4 to 7.7 times higher than previous work. The 407 Mpixels/W power efficiency is achieved, and 94% on-chip SRAM size and 79% external memory bandwidth are saved by the proposed techniques.     

Pitch synchronous 1st-order linear d.p.c.m. system

A system called p.s.f.o.l.d. is described which exploits the correlation between successive pitch periods of a speech signal. This system is a differential one and can employ various types of encoders. We describe a p.s.f.o.l.d. system using a 1st-order d.p.c.m. encoder and show that for a speech utterance this system has a peak signal/noise ratio which is 6 dB larger, and has an increase in dynamic range of 13 dB, compared with a 1st-order d.p.c.m. codec.     

基于编码器插值技术的光衰减器电机定位系统

介绍了一种采用编码器插值技术的光衰减器电机定位系统的设计方法.采用编码器检测角度位置很方便.对于高精度的检测,可以使用高分辨率的编码器.但是随着编码器分辨率的提高,其生产难度很大,成本将大幅增加.通过采用插值技术,将角度进一步细分,不必更换编码器,在成本增加不多的情况下,大幅提高系统的分辨率.系统采用CPU驱动直流无刷电机转动,编码器输出的正余弦信号指示电机的位置.正余弦信号一方面用于脉冲计数,另一方面用于输入A/D转换器进行插值.理论计算以及实际测试证明该方案结构简单、精度高、性能稳定、价格低廉.     

A VLSI High-Performance Priority Encoder Using Standard CMOS Library

A novel high-performance priority encoder design using standard CMOS library cell is proposed. The new encoder design implementation accommodates both high- and low-priority functionalities with scalable design structure through a special prefixing scheme. The prefixing scheme is applied to minimize the entire propagation delay and exploit the shared hardware between the high- and low-priority evaluation logics circuitry. The proposed encoder shows significant improvement in terms of speed, robustness for top-level floor plan routing, and modularity with pattern structure in compared to the existing encoder designs. Simulation results are conducted for different encoder inputs through 0.15-$muhbox m$TSMC CMOS technology, where 32-bit priority encoder is used as a test vehicle for comparison improvement measurements. The expected results show that the 32-bit encoder is operating at a maximum of 667-MHz operating frequency with total count of 1106 transistors and a maximum power consumption of total 13.8 mW.     

并行AVS实时编解码器设计与实现

介绍了一种并行AVS实时编码器的设计,它包括音视频数据输入、音视频编码、传输流系统复用器、输出和控制部分,其中重点介绍了视频编码器和传输流系统复用器的设计和实现.实验结果证明,实现标清AVS实时编码器是可行的.     

一种LDPC码实时编码器的设计与实现

设计并实现了一种基于TMS320C6416高性能通用DSP的LDPC码实时编码器,详细介绍了系统的实现方案和工作流程.为解决LDPC码编码复杂度大,且要保证编码的实时性问题,采用了具有较低编码复杂度的准循环LDPC码的编码结构和基于TMS320C6000的软件优化技术.仿真结果表明,该编码器可实现7Mb/s以上的信息编码速率.     

循环汉明码编译码器的设计与FPGA实现

分析了循环码的特性,提出一种循环汉明码编译码器的设计方案。编译码器中编码采用除法电路,译码采用梅吉特译码器,易于工程应用。对编译码器在FPGA上进行了实现,通过参数化设置,具有较高的码率,适用于(255,247)及其任意缩短码的循环汉明码,并给出了译码器的仿真和测试结果。结果表明:编译码器运行速率高、译码时延小,在Virtex-5芯片上,最高工作时钟频率大于270 MHz。在码组错误个数确定的系统应用中,可以有效降低误码率,一般可将误码率降低一个量级。实践表明,该设计具有很强的工程实用价值。