Ion-implanted microwave field-effect transistors in GaAs

Microwave field effect transistors have been fabricated in gallium arsenide by using sulfur ion implantation directly into semi insulating Cr doped substrates to produce the channel region, eliminating the need for growth of an epitaxial layer. This implantation method has been used to produce 0·25 μm thick, n-type layers with uniform thickness and carrier concentration, and carrier mobility ranging from 2410 to 3620 cm²/V sec in different samples. Because of the uniformity, FET's fabricated in these layers have exhibited reproducibility of transconductance and pinchoff voltage from device to device on a wafer to better than ±10 per cent. Cr doped GaAs of commonly available quality was found to be satisfactory for FET fabrication, although minimum Cr compensation is desirable to obtain highest mobility. S parameter measurements of microwave characteristics indicated a projected f_max = 20 GHz but transducer gain cutoff occurred at approximately 7 GHz because of impedance mismatch and package parasitics.     

Ion-implanted super-grain transistors

This paper discusses the use of ion implantation to develop a viable high-yielding process for fabricating super-gain transistors for integrated circuits. The authors discuss the fabrication processes utilized, the pertinent device physics, the manufacturing tradeoffs, and present the results obtained for two different ion-implanted base integrated-circuit processes.     

Contact conductivity notch effects in indium phosphide microwave oscillators

Device length independent oscillations between 1 and 5 GHz in bulk InP microwave oscillators are plausibly explained as a transferred electron oscillation which is contained in a ‘conductivity notch’. The avalanche breakdown capabilities of GaAs and InP are compared with the aid of a simple inhomogeneity model.     

Indium gallium arsenide microwave power transistors

Depletion-mode InGaAs microwave power MISFETs with 1-μm gate lengths and up to 1-mm gate widths have been fabricated using an ion-implanted process. The devices employed a plasma-deposited silicon/silicon dioxide gate insulator. The DC current-voltage (I -V) characteristics and RF power performance at 9.7 GHz are presented. The output power, power-added efficiency, and power gain as a function of input power are reported. An output power of 1.07 W at 9.7 GHz with a corresponding power gain and power-added efficiency of 4.3 dB and 38%, respectively, was obtained. The large-gate-width devices provided over twice the previously reported output power for InGaAs MISFETs at X-band. In addition, the first report of RF output stability of InGaAs MISFETs over 24 h period is also presented. An output power stability within 1.2% over 24 h of continuous operation was achieved. In addition, a drain current drift of 4% over 10⁴ s was obtained     

Measurement of the velocity-field characteristic of indium phosphide by the microwave absorption technique

The electron velocity-field characteristic has been determined for a large number of samples of InP by the microwave absorption technique. The values obtained for the electric field at the peak of the velocity-field curve are corrected for relaxation effects by comparison with a computer simulation, and the resulting values lie in the range 7.2-9.8 kV/cm^-1. The corrected negative dynamic mobility just beyond the peak velocity varied between 0.3 and 0.5 of the low-field mobility.     

Ion-implanted complementary MOS transistors in low-voltage circuits

Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.     

A two-dimensional analysis of indium phosphide junction field effect transistors with long and short channels

A two-dimensional analysis of indium phosphide junction field effect transistors with long and short gates is presented. The two devices are shown to have properties similar to those of gallium arsenide JFETs. The short gate device has a negative resistance region at low drain voltages which is absent in the long gate device. The negative resistance region is determined by the distribution of the drift velocity along the conducting channel, and the resulting distribution of the electron charge. A field dependent mobility is used, and its effect on current saturation is discussed. The electrostatic charge distribution and electric field distribution are calculated for both devices, and are shown in graphic form.     

Reading light-optoelectronics on indium phosphide

In the future every house could be served by a single optical fibre which will carry basic telephony plus a wide range of broadband services such as video, videophone and high definition TV. The author discusses optoelectronic circuits (OEIC) as cheap optical receiver components. The construction and operation of OEIC are described and the use of them in optical receivers is discussed     

High-field transport in indium phosphide

Theoretical estimates of intervalley scattering rates in InP are used to determine velocity/field curves. The results do not support the 3-level model of high-field transport in this material.     

Transient annealing of indium phosphide

Thermal treatment of semiconductor samples in the range ∼ 650 to 900°C is an integral part of planar device processing for the activation of implanted ion species. This letter describes a rapid annealing procedure for the short-term treatment of such implants, which from data obtained on InP is seen to result in high activation efficiencies and mobilities ∼ 85 percent and 2600 cm²/V.s, respectively, while at the same time minimizing surface degradation and bulk impurity redistribution.     

Zone melting of indium phosphide

Bulk indium phosphide crystals have been prepared by zone melting with dislocation densities 104 ≤ N_d ≤ 105 cm^-2. The residual impurity level in nominally undoped crystals and the dopant distribution in Cd-, Sn- and Ge-doped zone melted ingots, as revealed by spark source mass spectrometric analyses, indicate a strong interaction between segregation at the solid/liquid interface and vapor transport. The effective distribution coefficients for Sn and Ge in zone melted InP are k_e(Sn) = 0.3 and k_e(Ge) = 0.4. The free electron concentration measured in the middle section of nominally undoped ingots is N_D-N_A = 1.9 × 10¹⁵ cm^-3 corresponding to a Hall mobility Μ_e = 3263 cm^2V-1sec^-l.     

Electron transfer in indium phosphide

Evidence for 2-level transfer in indium phosphide based on determinations of threshold field is shown to be inconclusive.     

Indium phosphide accumulation-mode field-effect transistors

Enhancement-type insulated gate field-effect transistors made of semi-insulating InP depend on the surface accumulation of electrons induced by a positive gate voltage and an equilibrium surface potential whose sign and magnitude are considered to be functions of the difference between charged surface donor and occupied acceptor states.     

Current gain collapse in microwave multifinger heterojunctionbipolar transistors operated at very high power densities

The rapid development of heterojunction bipolar transistor (HBT) technologies has led to the demonstration of high power single-chip microwave amplifiers. Because HBTs are operated at high power densities, the ultimate limits on the performance of HBTs are imposed by thermal considerations. The authors address a thermal phenomenon observed when a multifinger power HBT is operating at high power densities. This phenomenon, referred to as the collapse (of current gain), occurs when suddenly one finger of the HBT draws most of the collector current, leading to an abrupt decrease of current gain. A quantitative model and the condition separating the normal operation region and the collapse are presented. Critical difference of the collapse in the constant l _b and constant V_be modes of operation is discussed for the common-emitter l-V characteristics. The collapse in the common-base l-V characteristics and its relationship with avalanche breakdown are also described. A solution to eliminate the collapse is experimentally verified     

Ion-implanted FET for power applications

High-energy ion implantation is coupled with the conventional planar technology to realize a silicon FET for power application. This device known as "Gridistor" is a multichannel FET with a p-type buried as gate. Boron implantation at various energies (600-900 keV) through a metallic mask are used to do a high-doped p-type gate layer, 0.8 µ thick and buried 1 µ below the surface. Since there is no implantation induced defects in the active regions of the device, low annealing temperature can be effectively used. As a consequence, the pattern sharpness is only limited by the definition of the mask. Using ion-etched gold layer as mask, 1 µ wide channels are made in a reproductible way. Few test structures have been made to check the behavior of implantation and planar technologies by measuring their capaci tances, transconductance, and I-V characteristics.     

Improved circuit-device interface for microwave bipolar power transistors

Several improvements in the mounting and interconnection of bipolar microwave power transistors are described. A plated heat sink applied to thinned transistor pellets decreases the junction temperature for a given dissipation level by approximately a factor of 2. A new, low-parasitic-BeO carrier provides improved power sharing between cells and better high-frequency performance as illustrated by a CW power output of 4 W at 5 GHz with 6-dB gain. Finally, a new etched-line interconnection system is discussed that promises to become a highly reproducible, low-cost replacement for the widely used, but troublesome, multiple wire bonds.     

Ion-implanted threshold tailoring for insulated gate field-effect transistors

This paper develops a general threshold equation for long-channel insulated gate field-effect transistors which accounts for the effects of ion-implant profiles used in threshold tailoring. Although any integrable function used to describe the nonuniform doping will yield an analytical expression for threshold, a Gaussian function is chosen because it accurately describes the implanted profile following proper annealing, regardless of subsequent high-temperature steps during fabrication. Most profiles of interest are quasi-neutral, i.e., the spatial dependence of the majority carriers in the undepleted bulk is adequately described by the doping profile, but the threshold equation is shown to be an excellent approximation for non quasi-neutral profiles as well. Comparison with experimental results show the analytical expression to be in good agreement with data over a wide range of implant conditions and starting substrate resistivity.     

Dielectric constant of semi-insulating indium phosphide

Results are given on precision measurements of the relative dielectric constant of semi-insulating indium phosphide. It is concluded that the static value is within less than 0.5% of 12.55 based on a statistical average of a large number of measurements on several material samples.     

Electrical properties of transmutation-doped indium phosphide

Experimental results of studying the process of transmutation doping of InP single crystals by irradiating with nuclear-reactor neutrons are reported; the possibility of doping with tin in a wide range of concentrations and obtaining the concentration of free electrons as high as 2×10¹⁹ cm^?3 is demonstrated. Electrical properties of InP and their behavior under irradiation and in the course of subsequent heat treatments were studied. The prospects for utilization of the nuclear-transmutation method for doping are assessed.