A micropower, small input-to-output delay, high-voltage bipolar driver/demultiplexer IC

Describes a 2.6/spl times/2.6 mm bipolar driver/demultiplexer integrated circuit used to selectively switch one of six off-chip MOS devices. A carefully chosen chip architecture coupled with novel circuit techniques has reduced power consumption by more than two orders of magnitude over currently available micropower drivers that offer comparable performance. A low-voltage bipolar process (BV/SUB CEO/>20 V) that utilizes an extra deep n/SUP +/ diffusion (d-n/SUP +/) combines I/SUP 2/L and linear circuitry to achieve a micropower function (<100 /spl mu/W) with small input-to-output delay (<400 ns) and high-voltage capability (40 V max).     

Considerations for high-speed and analog-circuit-compatible I/SUP 2/L and the analysis of Poly I/SUP 2/L

Expressions are derived for minimum propagation-delay time and DC operational conditions in the I/SUP 2/L circuit configuration, and are applied to several kinds of I/SUP 2/L limitations. 1) Ultimately achievable (roughly 0.34 ns, fan-out of 2) and reasonably expected minimum propagation-delay values (0.75-1.0 ns considering simple n-p-n limitations) are estimated. 2) Speed improvements of the standard I/SUP 2/L structure via doping level adjustment is shown to be minimal (it is primarily useful for ensurance of DC operation). 3) Requiring analog compatibility further constrains performance; a figure of merit of about 1 to 2 V/ns is derived and experimentally confirmed for the product of analog device BV/SUB CBO/ and I/SUP 2/L speed for standard epitaxial I/SUP 2/L processing. Radical techniques using dual buried layers, dual epitaxial layers, or Poly I/SUP 2/L offer considerably enhanced performance by attacking the parameter with primary leverage on these tradeoffs: base-to-buried layer spacing W/SUB epi/. Analysis of Poly I/SUP 2/L reveals specific advantages.     

An isolated vertical n-p-n transistor in an n-well CMOS process

Isolated vertical n-p-n transistors were fabricated by a modified 5-/spl mu/m n-well CMOS process. The modification included a decrease in the p/SUP +/ source and drain implant dose and an increase in the final anneal time, but no extra processing steps of masks were required. The n-p-n transistors had generally good characteristics, with H/SUB FE//spl ap/600 and BV/SUB CEO//spl ap/40 V, while the MOS characteristics were unchanged.     

Linear compatible I/SUP 2/L technology with high voltage transistors

A technology is proposed in which it is possible to realize both I/SUP 2/L circuits and linear transistors with V/SUB CBO/ of 60 V. The essential step in such a technology is an additional n/SUP +/-flat diffusion. The technological parameters are derived. From measurements on wafers processed in the outlined technology. The author established functioning I/SUP 2/L elements and high voltage transistors.     

(MI)/SUP 2/L: multiinput-multioutput integrated injection logic

The (MI)/SUP 2/L structure will be discussed, which is a combination of CHL/CHIL and I/SUP 2/L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I/SUP 2/L schemes. The gate consists of a lateral n-p-n transistor with intermediate collectors and a Schottky inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to a standard bipolar process of 6 /spl mu/m epi thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of 0.07 pJ and a minimum delay of 17 ns at 0.38 pJ. The improved device parameters, packing density, and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS flip-flop.     

I/SUP 2/L current gain design

A DC model useful for I/SUP 2/L upward current gain (/spl beta//SUB /spl mu//) design is described. An expression for /spl beta//SUB /spl mu// is obtained in terms of model parameters which are related to device morphology. Design parameters are identified for a standard bipolar technology and a minimum geometry cell.     

Second generation I/SUP 2/L/MTL: a 20 ns process/structure

A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully been designed, characterized, and demonstrated fully functional over a wide current range and the military temperature range of -55 to 125/spl deg/C. Performance is measured using an in-line five-collector gate having one end injector. The gate performed with the following characteristics at 100 /spl mu/A injector current: /spl beta//SUB U//SUP eff//spl ges/4 for all collectors at 25/spl deg/C and /spl ges/2.5 at -55/spl deg/C, /spl alpha//SUB rec///spl alpha//SUB F//spl cong/0.58 and /spl tau/~/SUB d/=18-20 ns from -55 to 125/spl deg/C, and a speed-power product of 1.4 pJ at 25/spl deg/C. At low injector currents, a constant speed-power product of 0.36 pJ at 25/spl deg/ was obtained.     

I/SUP 2/L and high-voltage analog circuitry on the same chip: a comparison between various combination processes

Comparative experiments are presented for the I/SUP 2/L properties of: method (a) a standard 25 V BV/SUB CE/ analogue process; method (b) a modification of the same process with an extra N/SUP +/ diffusion giving deeper I/SUP 2/L collectors; method (c) a modification giving a more shallow I/SUP 2/L base; and method (d) two modifications involving a selective doping of the epi layer in the I/SUP 2/L part. Aside from the additional step in each method all process parameters, as well as the I/SUP 2/L gate geometry are kept the same. It is found that processes (d) give significantly higher effective gain for the n-p-n switching transistor than the other methods. The optimum speed is also higher for these processes, but the other methods have a lower power-delay product at low current level. THe reasons for the differences are analyzed. For one of the processes (d) the effect of a shallow versus deep N/SUP +/ guard ring is discussed, and the sensitivity to variations in process parameters is commented on.     

A 35 ns 2K /spl times/ 8 HMOS static RAM

This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/.     

Current regulators for I/SUP 2/L circuits to be operated from low-voltage power supplies

A new bandgap current reference is described which can be used to control the injector current of I/SUP 2/L circuits for supply voltages down to about 1 V. For small currents the total injector current is obtained as a mirror of the reference current. For large injector currents the current control is performed by a series regulator which compares the injector current of one I/SUP 2/L gate to the reference current. The described reference current can be adjusted to give a variation with temperature of about 60 ppm//spl deg/C over the temperature range -10 to +70/spl deg/C. However, in some applications a nonzero, but well controlled temperature coefficient is desired. It is shown how a temperature stable ring oscillator with I/SUP 2/L gates can be constructed by tailoring the temperature dependence of the supply current appropriately.     

Improved Schottky clamped (T/SUP 2/L) circuits

Al-Si Schottky clamped transistors used as fast switching signal devices or in integrated circuits are superior to gold-doped transistors for such parameters as low-level current gain, leakage current I/SUB CO/, and propagation delay t/SUB pd/. A digital application is used to show how some of these parameters can be optimized for a T/SUP 2/L circuit, providing high switching speed (t/SUB pd/ 4 to 5 ns) and a 40-percent better worst-case low-level noise margin than the usual gold-doped T/SUP 2/L circuit.     

Logic gates with shaped Josephson junctions

Long (L//spl lambda//SUB j/>5) in-line Josephson junctions, with varying width along the length L of the device, are investigated as logic gates (/spl lambda//SUB j/ being the Josephson penetration depth). The devices realized have an asymmetric threshold characteristic with almost suppressed sidelobes, providing good logic gain and permitting logic fan-in with multiple control lines. Optimum conditions are found for junctions with width varying approximately sinusoidally along the device length. The so-called shaped junctions are incorporated in various flip-flop circuits to evaluate the transfer time and transfer efficiency of loop circuits, and in a self-resetting inverter circuit to demonstrate the feasibility of self-resetting logic. The principle of current steering and the relatively large operating currents (I/SUB G//spl sime/6 mA) make the circuits suitable for medium-speed applications such as in the decode and control logic of a main-memory chip. For a fan-out of four, the minimum circuit delay is 300 ps, resulting in a power-delay product in the order of 3/spl times/10/SUP -15/ J.     

Properties of Be-implanted planar GaAs p-n junctions

The fabrication and characteristics of planar junctions in GaAs formed by Be ion implantation are discussed. The critical processing step is shown to be the use of a carefully deposited oxygen-free Si/SUB 3/N/SUB 4/ encapsulation during post-implantation annealing. Forward and reverse characteristics are presented for Be-implanted junctions formed by encapsulating with SiO/SUB 2/, Si/SUB x/O/SUB y/N/SUB z/, or Si/SUB 3/N/SUB 4/ layers prior to annealing at 900/spl deg/C. Junctions which exhibit leakage current density of ~2/spl times/10/SUP -7/ A/cm/SUP 2/ at 80 V reverse bias and breakdown voltage >200 V have been fabricated using RF-plasma deposited Si/SUB 3/N/SUB 4/ layers as the encapsulant.     

15-nm base type-II InP/GaAsSb/InP DHBTs with F/sub T/=384 GHz and a 6-V BV/sub CEO/

Type-II InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a 15-nm base were fabricated by contact lithography: 0.73/spl times/11 /spl mu/m/sup 2/ emitter devices feature f/sub T/=384GHz (f/sub MAX/=262GHz) and BV/sub CEO/=6V. This is the highest f/sub T/ ever reported for InP/GaAsSb DHBTs, and an "all-technology" record f/sub T//spl times/BV/sub CEO/ product of 2304 GHz/spl middot/V. This result is credited to the favorable scaling of InP/GaAsSb/InP DHBT breakdown voltages (BV/sub CEO/) in thin collector structures.     

Overall stability factor of linear two-ports in terms of scattering parameters

Stability conditions for linear active two-ports in terms of classical two-port parameters, which include the terminations, have been derived earlier but the analogous result in terms of scattering parameters apparently is not known. It is shown that the stability condition is 1-|r/SUB G/s/SUB 11/|/SUP 2/-|r/SUB L/s/SUB 22/|/SUP 2/ + |r/SUB G/r/SUB L//spl Delta/|/SUP 2/>2|r/SUB G/r/SUB L/|.|s/SUB 12/s/SUB 21/| from which the overall stability factor is derived.     

Scaling I/SUP 2/L for VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I/SUP 2/L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I/SUP 2/L devices with geometries >1 /spl mu/m is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I/SUP 2/L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted.     

Monolithic analog multiplier-divider

The design of a precision general-purpose monolithic analog multiplier-divider based on the principle of the variable transconductance of bipolar transistors is described. The device has two new aspects: first, an eight-transistor multiplier-divider core, and second, an improvement in the accuracy and high-frequency behavior of the input and output circuits having monolithic conversion resistors. The transfer function /spl nu//SUB w/=/spl nu//SUB x//spl nu//SUB y///spl nu//SUB z/ is only dependent on external voltages. An advantage of the multiplier-divider over a multiplier with a fixed internal voltage reference is that the external signal voltages can be accurately related to the relevant reference voltage. Moreover, the additional divider input enlarges the application field. The maximum signal voltages are /spl plusmn/10 V. The untrimmed inaccuracy is typically 2 percent. The nonlinearity is /spl plusmn/0.1 percent. The bandwidth is 6.5 MHz, and the slew rate is 50 V//spl mu/s.     

An 8-MHz CMOS subranging 8-bit A/D converter

A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.     

Noise-induced error rate as limiting factory for energy per operation in digital ICs

Due to the steady progress in computer technologies over the past years, the physical limits of the energy required per logical operation are assuming increased practical significance. Whereas earlier studies have considered only the elementary energies (e.g., kT, hv) or the power consumption during gate switching, the present work takes account of the random errors induced in an idealized gate by noise. The dependence of the minimum energy W/SUB I/ on the permissible error rate A is calculated for thermal noise. The result obtained, W/SUB I//spl ap/3.9 kT in (5A)/SUP -1/ for 10/SUP -7/>A>10/SUP -23/, is discussed regarding other limits in semiconductor circuits.     

An 8-bit, 5 ns monolithic D/A converter subsystem

Describes a 5 ns settling time digital-to-analog converter device, which has been designed for use in video speed successive approximation analog to digital converters. The chip includes a precision reference source with a 25 ppm per degree C average temperature coefficient and a high-speed comparator. The successive approximation approach, restricted to low-speed converters until now, has the advantages of low cost and straightforward drive requirements. The achievement of the operating speeds described is dependent both on the circuit techniques used and the process employed. The DAC circuit, unlike most other devices, uses a multiple-matched current source array technique, which leads to a very linear, low glitch output. Without any form of trimming, most functional devices meet a /spl plusmn//SUP 1///SUB 2/ LSB differential and integral linearity specification, and many are /spl plusmn//SUP 1///SUB 4/ LSB or better.