Analysis and design of a new race-free four-phase CMOS logic

A four-phase dynamic logic, called the high-speed precharge-discharge CMOS (HS-PDCMOS) logic, is proposed and analyzed. Basically, the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and form the pipelined structure as well. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to partly verify the results of circuit analysis and simulation. It is shown that the HS-PDCMOS logic has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the logic has no clock skew, race, and charge redistribution problems. These advantages make the HS-PDCMOS logic very promising in high-speed complex VLSI design     

Mixed static and domino logic on the CMOS gate forest

In a semicustom design environment with unified transistor geometries, logic circuit optimization is achieved using an efficient physical circuit implementation. In particular, the semicustom realization of domino logic is demonstrated with a standard-cell and a multiplier design which are used to support the implementation of such a dynamic logic design style on a gate forest, which has a higher n count than p count. The mixture of complementary and dynamic logic allows the designer to improve the critical-path delay and to reduce the size of the layout. The domino standard-cell architecture supports multiple-output configurations and additional internal precharge. The operation time for a mixed static/dynamic multiplier is approximately 30% higher than that of the static version based on a carry select adder. This difference mainly affects the critical delay of the sign-extension path of the parallel adder array     

Noise in digital dynamic CMOS circuits

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits     

Thickness limitations of SiO2 gate dielectrics for MOSULSI

The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si₃N ₄ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current     

High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.     

GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 μm non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps     

Design for concurrent error detection and testability instorage/logic arrays

Storage/Logic Arrays (SLA's) represent a structured logic array approach to the design of VLSI sequential logic. Design for concurrent error detection and testability is complicated in these arrays by the presence of embedded memory elements and multiple levels of logic. A means of designing SLA's for ease of testability and concurrent error detection (CED) is provided in this paper. Test sets for static and dynamic CMOS circuits are described. Fault and error coverage is presented and performance and area costs are analyzed for example circuits. In addition, a means of implementing dynamic CMOS SLA's is presented and shown superior to previous NMOS, static CMOS, and dynamic CMOS approaches based upon power consumption and simplicity of design     

On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.     

Robust subthreshold logic for ultra-low power operation

Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic     

Clock-delayed domino for dynamic circuit design

Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is as easy to design with as static CMOS circuits from a logic design and synthesis perspective. Design tools developed for static CMOS are used as part of a methodology for automating the design of CD domino circuits. The methodology and CD domino's characteristics are demonstrated in the design of a 32-b carry look-ahead adder. The adder was fabricated with MOSIS's 0.8-μm CMOS process with scalable CMOS design rules that allow a 1.0-μm drawn gate length. Measurements of the adder show a worst case addition of 2.1 ns. The CD domino adder is 1.6× faster than a dual-rail domino adder designed with the same cell library and technology     

Locally clocked pipelines and dynamic logic

Micropipelines and most of its variants use a delay-insensitive controller to moderate a pipeline. In search of improved performance, we depart from the delay-insensitive model in favor of a bounded-delay model for the controller. In particular, we demonstrate how a general delay-insensitive controller for level-sensitive pipelines can be improved by assuming a bounded-delay model and taking advantage of delay information to make the controller faster and more efficient. The new control scheme is referred to as locally clocked (LC) control. A highly pipelined logic technique called LC dynamic logic is presented that combines the bounded-delay controller for their comments and suggestions. with a latching dynamic logic gate design. Simulations comparing LC control with its delay-insensitive counterpart are presented. Also, an 8 × 8 bit multiplier with a maximum frequency of 715 MHz for a 1 μm CMOS process that uses LC dynamic logic is presented     

一种静态电路兼容的4GHz 64位动态加法器设计

设计了一个与静态电路兼容的64位动态加法器,采用嵌入逻辑的动态触发器,以及多相位时钟技术,实现了与上、下级静态电路的接口.在加法器内部采用稀疏先行进位策略平衡逻辑路径长度以降低内部负载,提高性能.在STMicro90nmCMOS工艺下,该加法器可工作在4GHz时钟下,功耗45.9mW.     

Dynamic noise model and its application to high speed circuit design

A dynamic noise model is developed and applied to analyze the noise immunities of precharge-evaluate circuits. With cross-talk being the main source of noise injection in the circuit, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified through HSPICE simulation on DOMINO gates. Based on this dynamic noise model, a tool is developed and applied to find the static and dynamic noise-margins at various points in the circuit with the effects of charge share and power/ground bounce taken into account. Obtained noise-margins are translated into maximum allowable coupling capacitances between the nodes for different types of precharge-evaluate logic circuits. The results show the difference in dynamic noise immunities in different logic families. Accurate estimates of dynamic noise-margins and coupling capacitance bounds will help design robust CMOS circuits.     

A new family of semidynamic and dynamic flip-flops with embeddedlogic for high-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

Design and implementation of differential cascode voltage switchwith pass-gate (DCVSPG) logic for high-performance digital systems

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type of ratioless circuit, and it also provides superior performance with less power dissipation and better silicon area tradeoff. The basic DCVSPG design technique, the methodology for optimization, and synthesis of the pass-gate logic tree are described. The standard cell library development taking advantage of the dual-rail outputs of DCVSPG gates is also discussed. The performance comparisons with other existing pass-gate circuit techniques [complimentary pass-transistor logic (CPL), double pass-transistor logic (DPL), and swing restored pass-transistor logic (SRPL)] are presented. For more robust design, the DCVSPG with inverter buffers is also the best choice. A Viterbi macro design using the DCVSPG circuit technique is demonstrated. The process that the design is based upon is a 0.5-μm CMOS technology with 0.25-μm effective channel length and five layers of metal. This macro can run up to 500 MHz at the nominal process condition. In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance     

Gallium arsenide pseudo-dynamic latched logic

A new GaAs logic family, pseudo-dynamic latched logic (PDLL). is introduced. Compared with traditional static GaAs logic families, PDLL allows complex gate design with less power dissipation. In addition, it overcomes problems associated with charge degradation in the storage nodes in dynamic logic gates, and operates at relatively high temperatures. PDLL is self-latched which leads to the possibility of implementing compact pipeline systems     

A digital library for a flexible low-voltage organic thin-film transistor technology

This paper presents the design, fabrication and characterization of digital logic gates, flip-flops and shift registers based on low-voltage organic thin-film transistors (TFTs) on flexible plastic substrates. The organic transistors are based on the p-channel organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and have channel lengths as short as 5 μm and gate-to-contact overlaps of 20 μm. The organic TFT is modeled which allows us to simulate different logic gate architectures prior to the fabrication process. In this study, the zero-VGS, biased-load and pseudo-CMOS logic families are investigated, where their static and dynamic operations are modeled and measured. The inverter and NAND gates use channel length of 5 μm and operate with a supply voltage of 3 V. Static and dynamic master-slave flip-flops based on biased-load and pseudo-CMOS logic are designed, fabricated and characterized. A new design for biased-load dynamic flip-flops is proposed, where transmission gate switches are implemented using only p-channel transistors. 1-stage shift registers based on the new design and fabricated using TFTs with a channel length of 20 μm operate with a maximum frequency of about 3 kHz.     

A 1.0-GHz single-issue 64-bit powerPC integer processor

The organization and circuit design of a 1.0 GHz integer processor built in 0.25 μm CMOS technology are presented, a microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented     

Design optimization of JCMOS structures

JCMOS structures are based on merging an MOS capacitance, a JFET, and a bipolar transistor in an area of a single MOS transistor. The structure performs the basic operations of temporary storage, writing, and sensing of the stored data. It is used in DRAM, serial dynamic memory, and dynamic logic applications. In addition to the advantages of small size and high speed of operation, the use of the JCMOS structure to implement dynamic logic gates overcomes the problem of charge redistribution associated with conventional and domino CMOS logic circuits. In this paper, the JCMOS structure implementation using a retrograde p-well CMOS process is presented. An analytical model relating terminal voltages and currents to device dimensions and doping levels is derived. Simulation results are presented for both reading and writing modes of operation. A test cell was successfully fabricated to verify the principle of operation, and experimental and theoretical results are compared. A simplified lumped component equivalent circuit, to be used in circuit simulators such as SPICE, is presented, and its validity is investigated. The structure design requirements and procedure are presented. The model is used to optimize the design of the structure.