一种新的SOI制备技术:H~+离子注入、键合和分离

H＋离子注入Si片并经一定条件退火，可在Si片中形成埋层微空腔（microcavity）层，结合Si片键合技术，用智能剥离（Smart－cut）技术成功地制备了Unibond－SOI材料，并用扩展电阻（SRP）、卢瑟福背散射（RBS／C）和剖面透射电子显微镜（XTEM）等初步分析了其结构和电学性质．     

离子束合成SOI多层结构的研究

本文报道了借助高剂量离子注入、高温退火等技术获得不同类型SOI(Silicon on Insulator)材料的形成过程及其多层结构。以离子背散射和沟道技术、Auger能谱、透射电子显微镜、扩展电阻测试以及红外透射和反射等分析方法对这些SOI结构进行表征。比较了注O~+和注N~+两种SOI材料的优缺点。研究表明,高质量的SOI材料能够通过离子束合成技术获得。     

SOI材料片缺陷研究

SOI材料天然具有抗瞬时辐射的能力,文章介绍了SOI(绝缘体上硅)两类不同材料片SIMOX(注氧隔离法)SOI和Bonded Smart-Cut(智能剥离法)SOI的生产工艺流程。针对SOI材料片的特殊结构——顶层硅/埋氧绝缘层/衬底结构——对各个层次的缺陷进行详细的介绍,并对其在半导体工艺中产生的影响做了深入的阐述。结合目前实际工艺生产线的情况,将SOI材料片的检测分为两大类:可直接测试的表面及内部缺陷;间接的材料性能特征检测。同时提供了大量SOI材料片可行的测试原理,为工艺线SOI材料片缺陷检验提供了有效的方法。     

离子注入硅形成绝缘埋层的红外反射谱分析

高剂量、大束流的O~+或N~+注入硅中经高温退火后能形成质量很好的SOI(Silicon onInsulater)材料。在波数范围为5000—1500cm~(-1)的红外波段内,硅及SiO_2或Si_3N_4绝缘埋层对红外光均无吸收。采用计算机模拟不同处理条件下的样品在该波段范围的红外反射谱,得到了样品的折射率随深度的变化关系,所得结果与透射电子显微镜、离子背散射等方法所得的分析结果符合得很好。     

硅基光电子学中的SOI材料

SOI材料是近年来应用于硅基光电子学中的一种重要的光波导材料。本文首先简要介绍了常见的SOI材料的制备方法,包括注氧隔离（SIMOX-SOI）、硅键合背面腐蚀（BE-SOI）和注氢智能剥离（Smart Cut）等,并比较了它们各自的特点和优劣。其次介绍了SOI材料加工制造波导的基本工艺,包括光刻和刻蚀,其中刻蚀又分为干法刻蚀和湿法腐蚀。     

智能剥离SOI高温压力传感器

采用改进的RCA清洗工艺提高了硅片的低温键合质量,提出了一种积聚式缓慢退火剥离方法用于制备智能剥离SOI(Silicon On Insulator)材料,并用该材料成功地研制了双岛-梁-膜结构的SOI高温压力传感器.对SOI压力传感器的测量结果表明,当温度增加到150℃左右时,输出电压没有明显的变化,其工作温度高于一般的体硅压力传感器(其工作温度一般在120℃以下).测得所制备SOI压力传感器的灵敏度为63mV/(MPa*5V),比用相同版图设计和工艺参数制备的多晶硅压力传感器高约7倍多.     

基于Al2O3中间层的InP/SOI晶片键合技术研究

研究了基于Al2O3中间层的InP/SOI晶片键合技术.该方案利用原子层沉积技术在SOI晶片表面形成Al2O3作为InP/SOI键合中间层,同时采用氧等离子体工艺对晶片表面进行活化处理.原子力显微镜和接触角测试结果表明,氧等离子体处理使得晶片的表面特性更适于实现键合.透射电子显微镜和X射线能谱仪测试结果证实,采用Al2O3中间层可以实现InP晶片与SOI晶片的可靠键合.     

氮离子注入形成的SOI结构的研究

用透射电子显微镜(TEM)、扫描透射电子显微镜(STEM)和电子能量损失谱(EELS)对高剂量氮离子注入再经热退火所形成的硅-绝缘层(SOI)结构的纵断面进行了微区分析并测定了氮-硅元素浓度比沿深度的分布. EELS的分析证明了在绝缘层的多孔区中可能有一些以气体形式出现的氮分子. 利用EELS的低能等离子峰形成的能量选择像能够对硅和氮化硅进行相分离,并有助于估计可能引起短路的因素.     

智能剥离SOI高温压力传感器

采用改进的 RCA清洗工艺提高了硅片的低温键合质量 ,提出了一种积聚式缓慢退火剥离方法用于制备智能剥离 SOI (Silicon On Insulator)材料 ,并用该材料成功地研制了双岛 -梁 -膜结构的 SOI高温压力传感器 .对 SOI压力传感器的测量结果表明 ,当温度增加到 15 0℃左右时 ,输出电压没有明显的变化 ,其工作温度高于一般的体硅压力传感器 (其工作温度一般在 12 0℃以下 ) .测得所制备 SOI压力传感器的灵敏度为 6 3m V/ (MPa· 5 V) ,比用相同版图设计和工艺参数制备的多晶硅压力传感器高约 7倍多     

用等离子体浸没氦离子注入实现智能剥离

报道了用氦离子注入智能剥离形成SOI结构硅片的新技术,介绍了这种技术的工艺和用剖面透射电镜研究的结果。氦离子用等离子体浸没离子注入技术注入硅片中。     

Electron and hole mobility enhancement in strained-Si MOSFET's onSiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si_0.9Ge_0.1 layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer     

Crystallographic defects in thermally oxidized wafer bonded silicon on insulator (SOI) substrates

The crystalline quality of wafer bonded (WB) silicon on insulator (SOI) structures thermal treated in dry oxygen ambients has been investigated by means of transmission electron microscopy and defect etching. The main crystallographic defects present in the SOI layers are dislocations, amorphous precipitates, and oxidation induced stacking faults (OISF). The evolution of the OISFs with time and temperature has also been investigated. The main feature observed is that the OISF in WB SOI structures undergo a retrogrowth process at temperatures around T = 1195°C for times of t = 2h. This result is very similar to that recently reported for oxygen implanted SOI (SIMOX) but considerably different from that observed in bulk silicon. The experimental data fits nicely a model recently proposed for the retrogrowth of OISF in thin SOI layers. This model considers that the self-interstitial supersaturation is considerably reduced compared to bulk silicon due to the relative fast point defect recombination inside the top silicon layer.     

Reduction of leakage current at the gate edge of SDB SOI NMOStransistor

Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, ~2500 Å) and fully depleted (FD, ~800 Å) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES IIb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to ~pA and no hump was seen on the drain current curve     

Si（Ge）MOSFET器件微结构的研究

采用横断面的透射电子显微术，扫描电子显微术和高分辨电子显微学方法，研究了ＧｅＳｉ沟道ｐ－ＭＯＳＦＥＴ的微结构。观察表明，器件是由Ｓｉ基片／ＳｉＯ２非晶层／ＳＯＩＳｉ层／ＧｅＳｉ沟道层／超薄ＳｉＯ２非晶层／Ｓｉ细晶层／ＳｉＯ２非晶层／Ａｌ电极层等组成的；ＳＯＩＳｉ层工作区单晶性良好，很难找到缺陷，缺陷能效地被限制在工作两侧的缺陷聚集区；在ＳＯＳＳｉ层和ＧｅＳｉ沟道层之间存在着一些瓣状衬底，它可能是在     

Residual stress effect on electron mobility in ZMR-SOI

N-channel enhancement-mode MOSFETs have been fabricated in silicon-on-insulator (SOI) films prepared by both infra-red and laser zone-melting recrystallisation (ZMR). The SOI films are subjected to a lateral tensile stress due to the thermal expansion coefficient difference between silicon and silicon dioxide. The devices in the stressed films exhibit higher surface electron mobilities than those in bulk single crystal silicon. This phenomenon has been attributed to the influence of the stress through the change of the band structure as well as redistribution of carriers in k space.<>     

Multiple layers of CMOS integrated circuits using recrystallizedsilicon film

This letter presents a method to fabricate high performance three-dimensional (3-D) integrated circuits based on the conventional CMOS SOI technology. The first layer of transistors is fabricated on SOI and the second layer is fabricated on large-grain polysilicon-on-insulator (LPSOI), using oxide as the interlayer dielectric. The LPSOI film is formed by the recrystallization of amorphous silicon through metal induced lateral crystallization (MILC). The grain size obtained by the LPSOI process is much larger than the transistors and the transistor performance is similar to those fabricated on the SOI layer. Three-dimensional (3-D) CMOS inverters have been demonstrated with p-channel devices stacking over the n-channel ones     

A novel complementary N+-charge island SOI high voltage device

A new complementary interface charge island structure of SOI high voltage device (CNI SOI) and its model are presented. CNI SOI is characterized by equidistant high concentration n+-regions on the top and bottom interfaces of dielectric buried layers. When a high voltage is applied to the device, complementary hole and electron islands are formed on the two n+-regions on the top and bottom interfaces. The introduced interface charges effectively increase the electric field of the dielectric buried layer (E1) and reduce the electric field of the silicon layer (Es), which result in a high breakdown voltage (BV). The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI. EI = 731 V/μm and BV = 750 V are obtained by 2D simulation on a l-μm-thick dielectric layer and 5-μm-thick top silicon layer. Moreover, enhanced field E1 and reduced field Es by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm, respectively.     

Novel two-step SDB technology for high-performance thin-film SOI/MOSFET applications

A novel two-step oxided silicon wafer direct bonding process (TSDB) for fabricating high-quality SOI substrates is presented, which has no contamination, no complex thinning process and no subsurface damage. The fracture strength of the SOI/TSDB material is 180 kg/cm/sup 2/. SOI/TSDB NMOS and PMOS devices (0.8-3 mu m) have shown that the typical values of electron and hole surface channel mobility are 680 and 320 cm/sup 2//Vs, respectively. A high device transconductance and high on-off current ratio have also been obtained.<>     

激光结晶a-Si:H SOI离子注入和快速退火

本文对激光结晶a-Si∶H SOI结构砷注入和快速退火行为作了研究.a-Si∶H激光结晶有Lp-LCR,OD,FCR-2,FCR-1四个结晶区.用剖面电镜观察了结晶区的结构.扩展电阻测量表明Lp-LCR区中有两种扩散机制,即杂质在晶粒体内扩散和沿缺陷扩散.OD区中有三种扩散形式,除有上述两种以外,还有沿缺陷的扩散.首次比较了沿晶界和缺陷的扩散速度.