Checking Combinational Circuits by the Method of Logic Complement

Design of fully self-testing combinational circuits was considered. A theorem defining the conditions for guaranteed logic complement-based design of fully self-testing circuit was proved. Examples were presented.__________Translated from Avtomatika i Telemekhanika, No. 8, 2005, pp. 161–172.Original Russian Text Copyright © 2005 by Goessel, Morozov, V. Sapozhnikov, Vl. Sapozhnikov.     

Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic

Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The model-theoretic properties are exploited to handle the second-order nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof-theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way.We present a natural Kripke-style semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic (Information and Computation, Vol. 137, No. 1, 1–33, 1997), in which validity is validity up to stabilisation, and implication comes out as boundedly gives rise to. We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers. Following this second point of view an intensional semantics for proofs is presented which allows us effectively to compute quantitative stabilisation bounds.We discuss the application of the theory to the timing analysis of combinational circuits. To test our ideas we have implemented an experimental prototype tool and run several examples.     

OBDD在组合逻辑电路测试中的应用研究

传统的组合逻辑电路测试方法在搜索过程中都不可避免地要进行反向回溯,由于反向回溯的次数过多,往往会降低算法的效率,文中利用OBDD来表示电路中每个节点所代表的逻辑函数,把传统算法中的反向回溯过程转换为OBDD图的问题,从而加快了故障测试的速度,同时,OBDD在测试矢量集的生成以及必要值的确定中也显示出一定的优越性。     

组合逻辑电路的软错误率自动分析平台

为在设计阶段快速评估集成电路的软错误率,以指导高可靠集成电路的设计,提出一种适用于组合逻辑电路和时序逻辑电路组合逻辑部分的快速软错误率自动分析平台HSECT-ANLY.采用精确的屏蔽概率计算模型来分析软错误脉冲在电路中的传播;用向量传播和状态概率传播的方法来克服重汇聚路径的影响,以提高分析速度;使用LL(k)语法分析技术自动解析Verilog网表,使分析过程自动化,且使得本平台可分析时序电路的组合逻辑部分.开发工作针对综合后Verilog网表和通用的标准单元库完成,使得HSECT-ANLY的实用性更强.对ISCAS'85和ISCAS'89 Benchmark电路进行分析实验的结果表明:文中方法取得了与同类文献相似的结果,且速度更快,适用电路类型更多,可自动分析电路的软错误率并指导高可靠集成电路的设计.     

Logic Complement, a New Method of Checking the Combinational Circuits

A new method of functional checking of combinational circuits by the logic complement of the output function was proposed. A self-testing checker based on the 1-out-of-3 code was described. Results of experimental studies of the standard examples of the MCNC system were presented.     

Parallel Logic Programming for Problem Solving

We present a new model for parallel evaluation of logic programs. This model can exploit the main sources of parallelism that the language of logic expresses: Independent AND parallelism and OR parallelism, together with a secondary source emerging as a consequence of the Independent AND Parallelism: the producer/consumer parallelism. The efficiency is derived from the use of ordered structures for managing the information generated throughout the search process. The model is suitable for evaluating programs with a high degree of non-determinism because it never generates two processes for solving the same subgoal and hence it can exploit the same real parallelism generating a lower number of processes than other models. As an application example, we consider the Job Shop Scheduling problem. We report experimental results showing that logic programs can be designed that exhibit parallelism, and that the use of heuristic information translates into speedup in obtaining answers.     

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits

Radiation-induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft-error rates (SERs) in combinational circuits. In this work, we present methodologies to model soft errors in both the device and logic levels. At the device level, a hierarchical methodology to model neutron-induced soft errors is proposed. This model is used to create a transient current library, which will be useful for circuit-level soft-error estimation. The library contains the transient current response to various different factors such as ion energies, operating voltage, substrate bias, angle, and location of impact. At the logic level, we propose a new approach to estimating the SER of logic circuits that attempts to capture electrical, logic, and latch window masking concurrently. The average error of the SER estimates using our approach, compared to the estimates obtained using circuit-level simulations, is 6.5 percent while providing an average speedup of 15,000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.     

Parallel Logic Programming Systems on Scalable Architectures

Parallel logic programming (PLP) systems are sophisticated examples of symbolic computing systems. PLP systems address problems such as allocating dynamic memory, scheduling irregular computations, and managing different types of implicit parallelism. Most PLP systems have been developed for bus-based architectures. However, the complexity of PLP systems and the large amount of data they process raise the question of whether logic programming systems can still achieve good performance on modern scalable architectures, such as distributed shared-memory (DSM) systems. In this work we use execution-driven simulation of a cache-coherent DSM architecture to investigate the performance of Andorra-I, a state-of-the-art PLP system, on a modern multiprocessor. The results of this simulation show that Andorra-I exhibits reasonable running time performance, but it does not scale well. Our detailed analysis of cache misses and their sources expose several opportunities for improvements in Andorra-I. Based on this analysis, we modify Andorra-I using a set of simple techniques that led to significantly better running time and scalability. These results suggest that Andorra-I can and should perform well on modern multiprocessors. Furthermore, as Andorra-I shares its main data structures with several PLP systems, we conclude that the methodology and techniques used in our work can greatly benefit these other PLP systems.     

基于修复技术的组合电路进化设计算法研究

提出基于修复技术的组合逻辑电路快速进化设计算法。该算法利用候选电路在进化的初始阶段适应度增加很快的现象,先进化出一个功能大致正确的电路;然后转入修复过程并对不正确的输出进行修正,最终设计出功能正确的电路。为了能对进化出的有错误的电路进行修复,专门设计出简单而规整的修复电路的构造方法。附加的修复电路与进化生成的对大部分输入都能输出正确结果的电路结合在一起,形成最终的功能完全正确的电路。该方法极大地减少进化所需的时间。     

基于编码算法的组合逻辑电路最优化软件的设计与实现

在组合电路综合领域,逻辑最小化对电路面积及性能起到至关重要的作用。文章提出了一个新的产生本源蕴涵项的算法,并开发了一个最优化软件MININT,实验表明,它在运算速度和存储性能上都是高效的。     

组合电路随机测试的一种新方法

本文在随机测试的基础上提出了逆随机测试（ART）的新概念，在该测试序列的集合中各测试码之间的海明距离为尽可能的大，这样可以使不同的测试码检测到更多不同的故障，从则提高了测试效率和故障覆盖率。本文给出了构造逆随机测试序列（ARTS）的详细过程，并且严格证明了该序列的高效和正确性，同时还给出了用Benchmark和其它电路作为例子的实验结果。     

Genetic Parallel Programming: design and implementation

This paper presents a novel Genetic Parallel Programming (GPP) paradigm for evolving parallel programs running on a Multi-Arithmetic-Logic-Unit (Multi-ALU) Processor (MAP). The MAP is a Multiple Instruction-streams, Multiple Data-streams (MIMD), general-purpose register machine that can be implemented on modern Very Large-Scale Integrated Circuits (VLSIs) in order to evaluate genetic programs at high speed. For human programmers, writing parallel programs is more difficult than writing sequential programs. However, experimental results show that GPP evolves parallel programs with less computational effort than that of their sequential counterparts. It creates a new approach to evolving a feasible problem solution in parallel program form and then serializes it into a sequential program if required. The effectiveness and efficiency of GPP are investigated using a suite of 14 well-studied benchmark problems. Experimental results show that GPP speeds up evolution substantially.     

Checking Combinational Equivalence of Speed-Independent Circuits

We introduce the notion of combinational equivalence to relate two speed-independent asynchronous (sequential) circuits: a golden hazard-free circuit C ₁ and a target circuit C ₂ that can be derived from C ₁ through only combinational decomposition and extraction. Both circuits are assumed to be networks of single-output basic gates; multiple output gates such as arbiters, toggles, and dual-rail function blocks are not considered. We say that the circuits are combinationally equivalent if the decomposition and extraction preserves the essential functionality of the combinational blocks in the circuit and does not introduce hazards. The paper's focus is the bottleneck of the verification procedure, checking whether C ₂ is hazard-free. We show that C ₂ is hazard-free if and only if all of its signals are monotonic and acknowledged . We then show how cubes that approximate sets of reachable circuit states can be used to give sufficient conditions for monotonicity and acknowledgement. These sufficient conditions are used to develop a verification technique for combinational equivalence that can be exponentially faster than applying traditional, more general verification techniques. This result can be useful for verifying logic synthesis and technology mapping procedures.     

基于位串编码的遗传归纳逻辑程序设计

归纳逻辑程序设计是基于一阶逻辑的数据挖掘新方法。一阶规则挖掘是目标谓词和背景知识谓词对应的各种原子的复杂组合优化问题。该文根据Occam’s razor原理提出原子的位串编码,设计相应的遗传箅子,基于sequential covering策略提出采用遗传算法作为搜索策略的遗传归纳逻辑程序设计算法GILP。在连通图问题和gcd问题上验证算法的可行性。     

自适应主从式并行遗传算法在区间非线性规划问题求解中的应用

讨论了区间参数非线性规划问题．通过引入决策风险因子的概念，提出了一种不确定性非线性规划的一般命题形式．为求解该命题形式，提出一种自适应主从式并行遗传算法，该算法可以满足大规模优化问题的求解实时性要求，具有全局收敛性能．相对于常规主从式并行遗传算法，该算法通过动态调整从机的计算负荷，有效地解决了从机间计算负荷不均衡分布的问题．仿真结果表明了该自适应主从式并行遗传算法的可行性．     

基于多目标自适应遗传算法的逻辑电路门级进化方法

提出一种改进的遗传算法,通过网表级编码、多目标评估和遗传参数自适应等措施,可依据多个设计目标,以较少的运算量自动生成和优化逻辑电路．在数字乘法器、偶校验器等进化设计实验中,通过比手工设计和同类方法更优的新奇设计结果展示了该方法的有效性和先进性．     

带黑盒组合电路的等价性验证

为了在早期阶段发现电路设计错误,需要对包含未知部分的实现电路和规范电路进行等价性验证.本文提出了一种"分而治之"的方法,把电路划分成若干子电路,使用四值逻辑模拟技术对电路未知部分进行量化,然后对子电路的合取范式进行可满足性验证.这种方法增强了算法的错误检测能力,通过在ISCAS'85基准电路和10个简单组合电路上得到的两组实验数据表明了此算法的有效性和可行性.