A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).     

A multicarrier GMSK modulator with on-chip D/A converter for base stations

A multicarrier Gaussian minimum shift keying (GMSK) modulator with a 14-bit on-chip digital-to-analog (D/A) converter is presented. The design contains four GMSK modulators, which generate GMSK modulated carriers at the user-defined center frequencies. In wireless base stations, the modulated transmit signals are usually combined at the RF frequency after power amplification. The multicarrier modulator combines four GMSK modulated signals in the digital domain, thereby eliminating the need for an antenna microwave combiner. A new digital ramp generator and output power-level controller performs both the burst ramping and the dynamic power control in the digital domain. The maximum dynamic performance is obtained by multiplexing two D/A converters with output sampling switches. The digital multicarrier GMSK modulator is designed to fulfill the derived spectrum and phase-error specifications of the GSM 900/1800/1900 base stations for pico-, micro-, and macrocells. The die area of the chip is 26.8 mm/sup 2/ in 0.35-/spl mu/m CMOS (in BiCMOS) technology. Power consumption is 706 mW at 3.3 V with 52 MHz.     

A new interpolation technique for time interleaved \Upsigma\Updelta A/D converters

Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65?nm CMOS process.     

A Time-Interleaved $DeltaSigma$-DAC Architecture Clocked at the Nyquist Rate

This paper describes a delta–sigma ( $DeltaSigma$) digital-to- analog converter (DAC) architecture that combines a polyphase decomposition of the interpolation filter and a time-interleaved error-feedback $DeltaSigma$ modulator. Noise-shaped oversampling is achieved while clocking the digital circuitry at the Nyquist rate. The design of a third-order 4-bit modulator with eight times oversampling using the architecture is presented. Results from a prototype current-DAC driven by a VHDL simulation of the digital design at 2.66 GHz show that 56-dB linearity is achievable in 90-nm CMOS within a 1-V supply over a 155-MHz signal bandwidth making the architecture suitable for emerging ultra-wide-band and 60-GHz radio applications.      

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm².     

A multicarrier GMSK modulator

A multicarrier Gaussian minimum shift keying (GMSK) modulator has been developed and implemented. The design contains four GMSK modulators, which generate GMSK modulated carriers at the specified center frequencies. Utilization of the redundancy in the stored waveforms reduces the size of the GMSK trajectory look-up table to less than one-quarter of the original size in the modulator. Conventionally, the power ramping and output power level controlling are performed in the analog domain. A novel digital ramp generator and output power level controller perform both the burst ramping and the dynamic power control in the digital domain. The power control is realized by scaling the ramp curve, which follows a raised cosine/sine curve. The four GMSK modulated signals are combined together in the digital domain. The digital multicarrier GMSK modulator is designed to fulfil the spectrum and phase error specifications of the GSM 900 and DCS 1800 base stations     

A highly integrated analog front-end for 3G

This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intel's 0.18-/spl mu/m (SOC) flash+logic+analog (FLA) process technology using a 0.35-/spl mu/m feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm/sup 2/.     

A Class‐D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise

A class‐D audio amplifier for a digital hearing aid is described. The class‐D amplifier operates with a pulsecode modulated (PCM) digital input and consists of an interpolation filter, a digital sigma‐delta modulator (SDM), and an analog SDM, along with an H‐bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class‐D amplifier is implemented in a 0.13‐μm CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class‐D amplifier consumes 304 μW from a 1.2‐V power supply.     

14-bit 2.2-MS/s sigma-delta ADC's

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

A 14-bit, 10-Msamples/s D/A converter using multibit /spl Sigma//spl Delta/ modulation

A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-/spl mu/m CMOS technology and operates from a single 2.5-V supply.     

一种Σ-Δ A/D转换器抽取滤波器的设计

设计了一种Σ-ΔA/D转换器中的数字抽取滤波器。该滤波器应用于音频范围,采用多级多采样率的结构,由梳状滤波器、补偿滤波器以及两个半带滤波器组成。滤波器系数用标准符号编码实现,减少了乘法单元的使用。采用Simulink模拟过采样128倍的4位调制器输出;用Verilog编写用于测试的滤波器代码。在Matlab中分析滤波器输出码流,得到的信噪比为101 dB,能够满足高端音频A/D转换器的要求。     

A monolithic ΣΔ A/D and D/A converter with filter forbroad-band speech coding

The authors present a 5-V-only 14-b, 16 ksamples/s linear codec suitable as the audio part of a CCITT G722 codec. The device uses second-order sigma-delta modulation for both analog/digital (A/D) and digital/analog (D/A) conversion at 2.048 Msamples/s. A time-continuous modulator with integrated antialias filtering is used at the A/D side, obviating the need for an external antialiasing filter. The digital filters for decimation and interpolation are implemented with both a custom digital signal processor (DSP) and specialized hardware. The device was realized with 74000 transistors on a 31-mm² die in a 3-μm SACMOS technology. A dynamic range of more than 80 dB and a passband ripple of 0.3 dB were attained with A/D and D/A paths in cascade     

Mixed Cartesian feedback for Zero-IF WCDMA transmitter

In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA zero-intermediate frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback I/Q demodulator, and a digital stage adjusting the phase rotation around the loop. The whole system consumes 500 and 2.94 mW, respectively, for the analog and the digital part. System level simulation gave a maximum improvement of 35 dBc at 5 MHz from the carrier for the W-CDMA signal.     

A low-power triple-mode sigma-delta DAC for reconfigurable(WCDMA/TD-SCDMA/GSM) transmitters

A sigma-delta(Σ△) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio(SDR) system is presented.The conversion frequency,transfer function of the digital filter and theΣ△modulator,word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA,TD-SCDMA and GSM standards.TheΣ△DAC fabricated in SMIC 0.13-μm CMOS process occupies a die area of 0.72 mm~2,while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage.The measured SFDR is 62.8/60.1/ 75.5 dB for WCDMA/TD-SCDMA/GSM mode,respectively.     

Programmable SiGe BiCMOS low-pass filter for a multicarrier WCDMA base-station receiver

SiGe BiCMOS low-pass filter for a multicarrier WCDMA base-station receiver is described in this paper. The 4th-order Chebyshev filter with a 0.1-dB passband ripple is designed to drive a high-resolution A/D converter. The −3-dB frequency of the implemented filter can be programmed to four different bandwidths: 2.5, 5, 7.5, and 10 MHz depending on the number of received WCDMA channels. The filter achieves +9.7-dBV in-band IIP3, +20-dBV out-of-band IIP3, and 8.5-nV/√Hz input-referred noise density with 10-MHz bandwidth. The circuit uses a 2.5 V supply and has been fabricated in a 0.25-μm SiGe BiCMOS process.     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.     

A monolithic 2-b delta-sigma A/D converter

A monolithic 20-b analog-to-digital (A/D) converter using oversampling techniques which is implemented in standard 3-μm CMOS technology is described. The integrated circuit contains a fourth-order delta-sigma modulator and a digital finite-impulse-response filter and decimator. The modulator consists of a continuous-time chopper-stabilized front end, and a switched-capacitor loop filter and comparator. The dynamic range is 123 dB over a DC-to-500-Hz bandwidth, and the signal-to-noise-harmonic-distortion ratio is 126 dB. The chip consumes 125 mW power and has an area of 29.25 mm²     

A frequency-agile single-chip QAM modulator with beamformingdiversity

Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function     

A 56 mW Continuous-Time Quadrature Cascaded Σ∆ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.