SiGe沟道pMOSFET阈值电压模型

通过求解泊松方程,综合考虑短沟道效应和漏致势垒降低效应,建立了小尺寸S iG e沟道pM O SFET阈值电压模型,模拟结果和实验数据吻合良好。模拟分析表明,当S iG e沟道长度小于200 nm时,阈值电压受沟道长度、G e组份、衬底掺杂浓度、盖帽层厚度、栅氧化层厚度的影响较大。而对于500 nm以上的沟道长度,可忽略短沟道效应和漏致势垒降低效应对阈值电压的影响。     

亚0.1μm高K栅介质MOSFETs的特性

用二维模拟软件 ISE研究了典型的 70 nm高 K介质 MOSFETs的短沟性能 .结果表明 ,由于 FIBL 效应 ,随着栅介质介电常数的增大 ,阈值电区减小 ,而漏电流和亚阈值摆幅增大 ,导致器件短沟性能退化 .这种退化可以通过改变侧墙材料来抑制     

亚0.1μm高K栅介质MOSFETs的特性

用二维模拟软件ISE研究了典型的70nm高K介质MOSFETs的短沟性能.结果表明,由于FIBL效应,随着栅介质介电常数的增大,阈值电区减小,而漏电流和亚阈值摆幅增大,导致器件短沟性能退化.这种退化可以通过改变侧墙材料来抑制.     

应变SiGe沟道PMOSFET阈值电压模型

首先建立了应变SiGe沟道PMOSFET的一维阈值电压模型,在此基础上,通过考虑沟道横向电场的影响,将其扩展到适用于短沟道的准二维阈值电压模型,与二维数值模拟结果呈现出好的符合。利用此模型,模拟分析了各结构参数对器件阈值电压的影响,并简要讨论了无Sicap层器件的阈值电压。     

注F短沟MOSFET的抗热载流子损伤特性

研究了用注 F工艺制作的短沟 MOSFET的热载流子效应。实验结果表明 ,在栅介质中注入适量的 F能够明显地减小由热载流子注入引起的阈电压漂移、跨导退化和输出特性的变化。分析讨论了 F的抗热载流子损伤的机理     

掺Nd~(3+)玻璃微球阵列激光器的热学性能研究

为了研究二极管阵列抽运折射率匹配液冷却的掺Nd3+玻璃微球阵列增益区产生的热效应,采用FLUENT 6.3.26软件建立了激光器增益区流场的热-流-固耦合模型,利用有限元分析法,模拟分析了钕玻璃微球阵列的温度分布与自身尺寸、匹配液流速、微球层数和抽运频率的变化关系及其对热畸变的影响。由模拟结果可知,固体微球激光器的热恢复时间短,冷却效果与微球层数无关,流速增加对小尺寸微球的冷却效果无明显改善;当抽运频率为1Hz时,直径为2mm和4mm的微球增益区的单程最大光程差为3.1nm和51.9nm。结果表明,该构型激光器具有高效的冷却能力。这一结果对微球阵列激光器的热管理是有帮助的。     

掺Nd3+玻璃微球阵列激光器的热学性能研究

为了研究二极管阵列抽运折射率匹配液冷却的掺Nd3+玻璃微球阵列增益区产生的热效应,采用FLUENT6.3.26软件建立了激光器增益区流场的热-流-固耦合模型,利用有限元分析法,模拟分析了钕玻璃微球阵列的温度分布与自身尺寸、匹配液流速、微球层数和抽运频率的变化关系及其对热畸变的影响。由模拟结果可知,固体微球激光器的热恢复时间短,冷却效果与微球层数无关,流速增加对小尺寸微球的冷却效果无明显改善;当抽运频率为1Hz时,直径为2mm和4mm的微球增益区的单程最大光程差为3.1nm和51.9nm。结果表明,该构型激光器具有高效的冷却能力。这一结果对微球阵列激光器的热管理是有帮助的。     

不含短环的(n,3,k)LDPC码的几何构造方法

该文基于不含短环的(n,2, k)规则低密度奇偶校验(LDPC)码,提出了一种最短环长为8的(n,3, k)规则LDPC码的几何构造方法,该方法简单直观而有效。仿真结果显示,在AWGN信道中其具有明显优于随机构造的规则LDPC码的性能。     

基于LDPC码的单载波频域均衡系统

该文设计了一种联合判决-反馈均衡的单载波频域均衡(SC-FDE)系统,该系统用固定波形的短pn序列取代常规SC-FDE系统中的循环前缀(CP),并以多个短pn序列组成的长PN序列作信道训练从而解决快变信道的初始估计和跟踪问题。针对该系统,一种在时域内对接收的多个训练序列进行平均,然后提出了在频域对信道信息进行估计的信道训练算法,该算法与传统SC-FDE系统相比,其计算复杂度较低。另外,提出了一种增加纵向校验的LDPC码用于该系统中降低信噪比门限,提高系统的整体性能。仿真结果表明在多径衰落信道中,此系统可获得较为理想的结果。     

短彩信类业务实时信控新方法的研究与实践

当用户发起短彩信请求时,短彩信中心向实时信控系统发送鉴权请求,信控系统实时接收请求并实时收集用户发送特征结合预定信控策略识别是否为恶意用户并反馈鉴权结果,短彩信中心根据鉴权结果转发请求或拒绝发送.     

Deep submicrometer double-gate fully-depleted SOI PMOS devices: aconcise short-channel effect threshold voltage model using a quasi-2Dapproach

This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices     

Short-channel effect in fully depleted SOI MOSFETs

The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness     

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.     

Reverse short-channel effects on threshold voltage in submicrometersalicide devices

A reverse short-channel effect on threshold voltage caused by the self-aligned silicide process in submicrometer MOSFETs is reported. A physical model of lateral channel dopant redistribution due to the salicide process is proposed. The injection of vacancies and lattice strain during TiSi₂ formation causes defect-enhanced boron diffusion which results in a nonuniform lateral channel dopant redistribution and hence a threshold increase in short-channel devices. In addition to the small gate edge birds beak and the nonuniform oxidation-enhanced diffusion (OED) redistribution of channel dopant due to the polysilicon gate reoxidation, the self-aligned Ti silicide process can be major cause of the observed reverse short-channel effect in submicrometer MOSFET devices     

Modelling the threshold voltage of short-channel silicon-on-insulator MOSFETs

A simple analytical model for the threshold voltage of short-channel, thin-film, fully-depleted silicon-on-insulator MOSFETs is presented. The model is based on the analytical solution for the two-dimensional potential distribution in the silicon film, which is taken as the sum of the long-channel solution to the Poisson equation and the short-channel solution to the Laplace equation. The model shows close agreement with numerical PISCES simulation results. The equivalence between the proposed model and the parabolic model of Young (1989) is also proven.<>     

Analytical transient response and propagation delay evaluation ofthe CMOS inverter for short-channel devices

In this paper an accurate, analytical model for the evaluation of the CMOS inverter transient response and propagation delay for short-channel devices is presented. An exhaustive analysis of the inverter operation is provided which results in accurate expressions of the output response to an input ramp. Most of the factors which influence the inverter operation are taken into account. The α-power law MOS model, which considers the carriers' velocity saturation effects of short-channel devices, is used. The final results are in excellent agreement with SPICE simulations     

Modeling of Short-Channel Effects in Organic Thin-Film Transistors

We propose a model for short-channel organic thin-film transistors, which accounts for Poole-Frenkel field-dependent mobility and space-charge-limited current effects. The model is developed for devices operating in the linear regime, as well as in depletion and saturation regimes. Super linear output curves for low drain voltages, as well as nonsaturating currents, can be adequately described. Experimental results for short-channel P3HT devices have been fitted, showing good agreement with the proposed model.     

基于BSIM深亚微米级MOSFET短沟道效应建模和特征提取方法研究

本文基于BSIM标准研究了现代深亚微米级MOSFET器件的建模和特征提取方法,着重在于短沟道效应方面,其中测试样品由Micron^TM公司提供,最短沟道长度仅为0.16微米.内容包括一般短沟道效应、基板效应和漏极感应势垒降低效应(简称DIBL效应)等.研究表明,实验数据和BSIM模型结果较好吻合,证明文中方法的有效性以及较好的应用前景.     

Fault model for sub-micron CMOS ULSI circuits reliability assessment

A new fault model, based on the general Percolation theory applied to long-channel CMOS VLSI circuits, has been recently introduced. It was shown that a reliability risk appears only when process-related defects create a pattern independent current path in standby mode. An acceptable reliability risk defines pass/fail criteria. A screening technique, based on this model, presents a strong correlation between rejected devices and Early Failure Rate.In this paper, the general Percolation approach was applied to short-channel CMOS VLSI circuits. Unlike long-channel CMOS VLSI, defect-free short-channel CMOS VLSI circuits inherently have a pattern-independent standby current. It results from a short-channel MOSFET current in the off state. In this case, the defect-related component of this current might be released only by means of a multi parameter fail criterion. Experimental results that confirm this conclusion are presented and discussed. The Reliability Risk assessment technique employing this model shows a strong correlation between rejected devices and long term reliability for 32-bit 0.35 μM CMOS microprocessors.