比特串中值滤波

本文根据信号的分解性,对传统的多电平中值滤波(MF),提出了一种新的比特串中值滤波概念.其主要工作包括:(1)导出了比特串中值滤波的定义;(2)讨论了它的基本特性:(3)给出了它的实时信号处理电路结构和实验结果.     

基于FPGA的实时大窗口中值滤波器的设计

中值滤波在图像预处理阶段有着重要的应用,尤其是对于图像中脉冲噪声的滤除。传统的中值滤波算法都是通过对原数据按照大小排序,然后才能取出中值。但随着窗口尺寸的扩大,因数据增多而造成比较次数的激增,这成为制约大窗口中值滤波器实时性的一个瓶颈。针对这一问题,该文提出一种基于FPGA的25输入的实时中值滤波器的设计方法。无需对原数据进行大小排序,而是根据各比特平面的信息,重新生成一个中值,特别适合于FPGA实现。设计专用的位处理单元,简化了电路结构。通过三级查找表的方式,解决"多数表决器"耗时长的问题。实验结果表明,滤波器资源占用少,数据吞吐率高,延迟小,可满足任何窗口形状的滤波要求。     

便于硬件实现的去隔行算法研究

在比较几种去隔行算法的基础上,提出了两种便于硬件实现的去隔行算法:边增强窗函数算法和综合中值滤波算法.前一种算法采用双滤波器结构,既保证了图像的清晰度又使其边界锐利,获得了较好的视觉效果.后一种算法综合了几种中值滤波算法的优势,克服了原来算法去隔行时的缺点.软件仿真表明,图像的测评效果良好.两种算法的硬件实现方便,成本较低,具有实用价值.     

基于FPGA实现传真图像处理算法的方法

为了更快速地实现对传真图像的预处理,提出了以FPGA为平台的硬件传真图像处理算法.应用HDL硬件描述语言设计并实现中值滤波,边缘锐化,像域分离等图像处理算法.此外还提出了一种改进的快速中值滤波算法,通过验证表明,该算法不但加快了处理速度,也节省了硬件资源.     

基于菱形搜索的局部求精比特平面匹配图像稳定算法

提出一种基于菱形搜索的局部求精快速灰阶编码比特平面匹配和中值滤波运动校正的图像稳定算法,在保证匹配精度的前提下,大大降低了计算复杂度.仿真实验表明,本文算法简单,快速,有效,尤其适用于实时电子图像稳定.     

实时图像中值滤波算法及硬件实现

提出了一种基于灰度图像二维实时中值滤波算法,并给出该算法实现电路,及该算法与传统中值滤波算法的比较结果。     

图象中值滤波的硬件实现

文章简要介绍了几种中值滤波的算法，并对它们进行了计算机模拟和分析比较，根据算法对噪声的抑制作用及硬件实现的复杂程度，选取一种进行了硬件实验，给出了硬件电路的框图。     

嵌入式系统实时中值滤波的高效实现

为了满足嵌入式系统实时数字滤波的需要,针对抗脉冲干扰能力较好的中值数字滤波,提出一种存储量小、运算速度快的高效算法.该算法利用循环存储结构,在存储实时新数据的同时,自动剔除最老的旧数据,释放其所占用的存储资源,避免为新到来的数据申请存储资源.利用排序链表存储中值滤波的原始数据,避免了其他中值滤波算法在排序时必需的数据移动或交换,使中值滤波算法中的排序计算量降低到O(N)级,提高了算法效率.实测对比表明,提出的中值滤波算法的存储器使用量至多是传统中值滤波算法的37%,运算速度至少是Matlab函数库medfiltl()给定算法的2倍.     

复杂背景下红外小目标检测流水线快速预处理算法

提出了一种实现红外小目标检测的流水线预处理快速算法:在图像增强中,利用中值滤波和Laplace滤波抑制干扰和噪声;在阈值分割中,通过子图像动态阈值分离背景和目标.同时叙述了硬件流水线实现滤波和阈值的具体步骤和组织方式,做到了图像数据和处理结果的同步输入同步输出,最后给出实验结果.     

基于图像传感器的图像画质增强算法研究

针对图像在传输过程中易引入噪声、色彩质量下降、中值滤波导致图像细节丢失和均值滤波出现模糊等问题,提出了一种可以应用于CMOS图像传感器的图像画质增强和滤波算法.该算法对插值后的Bayer图像数据进行一维空间的增强和降噪处理,首先将图像从RGB空间转换到YUV空间,在Y通道上用改进的直方图均衡化方法实现图像明暗程度的对比度增强调节,对U、V通道采用分段式线性调节方法实现饱和度调节;然后对Y通道进行自适应降噪,对U、V通道进行加权中值滤波降噪,以满足后续处理对图像质量的要求;最后在Y通道上,采用基于Laplace算子的锐化掩模进行锐化处理,保证图像的细节清晰可见.实验结果表明:从图像视觉效果来看,相比单独使用中值和均值滤波,所提出的自适应滤波得到的效果更好,图像细节保存较好、模糊程度低、图像更为清晰,且色彩质量更高.通过对比峰值信噪比(PSNR),对混合噪声进行处理时,该滤波算法的PSNR优于中值和均值滤波,有效地抑制了噪声.整个算法在一维邻域空间进行,更容易在有限的硬件上实现较好的图像处理结果,满足小面积低功耗的要求.     

LMS adaptive filters using distributed arithmetic for high throughput

We present a new hardware adaptive filter architecture for very high throughput LMS adaptive filters using distributed arithmetic (DA). DA uses bit-serial operations and look-up tables (LUTs) to implement high throughput filters that use only about one cycle per bit of resolution regardless of filter length. However, building adaptive DA filters requires recalculating the LUTs for each adaptation which can negate any performance advantages of DA filtering. By using an auxiliary LUT with special addressing, the efficiency and throughput of DA adaptive filters can be of the same order as fixed DA filters. In this paper, we discuss a new hardware adaptive filter structure for very high throughput LMS adaptive filters. We describe the development of DA adaptive filters and show that practical implementations of DA adaptive filters have very high throughput relative to multiply and accumulate architectures. We also show that DA adaptive filters have a potential area and power consumption advantage over digital signal processing microprocessor architectures.     

一种快速CRC 算法①的硬件实现方法

介绍了CRC校验算法的硬件电路实现方法。CRC校验广泛应用于通信、存储系统，在串行CRC实现的基础上，对电路结构提出了改进的方案，并实现了CRC的并行计算，由此进一步可以适用于任意位数据宽度的数据输入情况。     

A Practical Parallel Architecture for Stacks Filters

Stack filters belong to the class of non-linear filters and include the well-known median filter, weighted median filters, order statistic filters and weighted order statistic filters. Any stack filter can be implemented by using the parallel threshold decomposition architecture which allows implementing their non-linear processing by means of a collection of identical binary filters (Boolean logic circuits). Although it is conceptually simple and useful to study the filter properties, this architecture is not practical for direct hardware implementation because as many as (M – 1) binary filters are required for a M-valued input signal and M is large in many applications.In this paper we introduce a new parallel architecture for stack filter implementations. The complexity is now proportional to the window width L of the filter, instead of to M. In most applications L is much smaller than M which translates into efficient hardware implementations. The attractive characteristic of ease of design exhibited by the threshold decomposition architecture is kept. In fact, for a given stack filter both in the conventional implementation and in the proposed one, the same binary filter is required. The key concept supporting the new architecture is a modified decomposition scheme which generates L binary signals for a multi-valued input. As an application example, a complex WOS filter is designed and prototyped in an FPGA.     

14位1.5625MHz的ΣΔA/D中的降采样低通滤波器的设计

介绍了带宽为 70 0kHz ,14 bitΣΔ模数转换器中的降采样低通滤波器的设计。在整个滤波器的设计中 ,从结构上和硬件实现上入手 ,对电路结构进行优化 ,减小电路实现的复杂性 ,从而降低功耗和面积。在此基础上 ,完成了电路设计 ,用 0 .6 μmCMOS工艺综合实现 ,仿真结果显示 ,性能满足设计指标。     

基于FPGA机载实时视频图形处理系统的设计

给出了某机载实时视频图形处理系统的硬件电路设计方案,以XC5VFX70T FPGA作为核心处理器,实现了对DVI及PAL等多种格式视频信号的解码、实时处理以及输出。系统电路设计简洁,具有较强的灵活性和扩展性。文中介绍了系统的硬件整体架构,论证了视频编解码模块和视频缓存模块的硬件设计方案。实际测试结果表明,系统能够流畅地...     

运动估计的分层搜索算法及FPGA实现

针对H．263，MPEG4 SP等低比特率的视频编码特点，在全搜索块匹配算法的基础上提出了一种适合在硬件上实现的运动估计新算法，以及实现这一算法的硬件结构。这种结构充分利用硬件资源，采用了并行结构及数据复用技术，从而大大节省计算时间。对于CIF格式的图像，运动矢量搜索范围为-16～ 15．5，帧速率可达25帧／s。     

Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters

The optimum architecture design and mapping of QRD-RLS adaptive filters can be achieved through filter architecture selections, look-ahead transformations, and hierarchical pipelining/folding transformations. In this paper, a relaxed annihilation-reordering look-ahead (RARL) architecture is proposed, and shown to be more power and area efficient than pipelined processing architecture which was considered the most area efficient. The filters with this architecture are based on relaxed weight-update through filtering approximation, where a filter tap weight is updated upon arrival of every block of input data, and are speeded up with annihilation-reordering look-ahead transformation. As a result of the computational complexity reduction, this architecture does not change the iteration bound and filter clock frequency, and leads to speed up with linear increase in power consumption, while the pipelined processing architectures result in speedup with quadratic increase in power consumption. Upon hardware mapping, this architecture is also more advantageous to achieve low area designs. Two design examples are presented to illustrate mapping optimization using above transformations. These results are important for mapping designs onto ASICs, FPGAs or parallel computing machines. The results show significant improvements in throughput, power consumption and hardware requirement. It is also interesting to show through mathematics and simulations that the RARL QRD-RLS filters have no performance degradation in terms of convergence rate.     

Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction

In modern systems, many well-known techniques (e.g., dynamic voltage and frequency scaling, job scheduling etc.) have been developed to achieve low power, high performance, appropriate quality-of-service or other specific purposes. Workload prediction is an extremely critical factor for bringing these techniques into full play. However, it is very difficult to accurately predict the workloads of upcoming tasks if they are varying drastically. In this paper, we propose a new hybrid fuzzy-Kalman filter and the corresponding area-efficient hardware architecture to accurately and quickly predict the workload with large variation. To decrease the hardware complexity while maintaining sufficient accuracy, the computation of Kalman Gain is simplified with a lookup table method. In addition, the workload and covariance values in Kalman filter are properly normalized and truncated to significantly reduce the bit length of hybrid workload predictor. Furthermore, a simplified fuzzy controller is developed to adaptively adjust the measurement noise covariance of Kalman filter so that the prediction error can be further lowered. Experimental results of real applications exhibit that the proposed hybrid fuzzy-Kalman filter can achieve lower prediction error and smaller hardware area when compared to previous workload predictors.     

A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic

This paper describes a gesteral-purpose digital-signal processor which is constructed with 4 bit bipolar microprocessor slices. The signal processor is microprogrammable and contains special features which allow it to employ distributed arithmetic. Hence, the processor can achieve high sampling rates without using a hardware multiplier unit. The processor's architecture is presented and its micro-order structure is examined. The processor wordlength is 16 bit; its basic cycle time, 300 ns; its data memory size, 2K words; its control store size, 256 x 56 bits. It consumes 48 W of power and has special address processing hardware. Experimental results with a twelfth-order digital filter are demonstrated. The signal processor is also compared with several other signal processors of its class described in the literature.     

A CMOS Implementation of a 1-Bit Multi-Cell Encoded—Cellular Neural Network

A new Cellular Neural Network (CNN)-based system has been implemented and tested to demonstrate the ability of this novel system to process large digital images more rapidly than its conventional CNN counterpart. The multi-cell encoded CNN processes the data of multiple single-data CNN cells within each multi-cell encoded cell enabling the new architecture it's advantages in loading, processing, unloading speed and in layout. A one bit (1B) 4-cell-encoded CNN was implemented to illustrate this new system. In this CMOS implementation, data of four neighboring conventional 1B CNN cells are encoded for processing within encoded cells. The CMOS circuits and circuit networks of one encoded cell are presented. Due to area limitations, each test chip includes the hardware for only one one-dimensional encoded cell. Experimental results of one-chip and two-chip 1B, multi-cell encoded systems are presented for connected-component detection and edge detection test cases. These results demonstrate the correct response of this implementation due to variations in template values, boundary values, and initial conditions. Interactions between encoded cell components and encoded cells are demonstrated for both dynamic and static responses. This CMOS implementation validates this new CNN architecture and provides a template for implementations using more advanced device technologies and circuits.