一种高增益低纹波的电荷泵电路

针对现有电荷泵存在的体效应、电荷回流等问题,提出一种高增益低纹波的电荷泵电路。该电荷泵采用两路互补的结构,减小了输出电压纹波;使用电位选择电路消除体效应,并使用两相低电平不交叠时钟避免电荷回流,提高了电压增益和转换效率。Hspice仿真结果表明,在级数同为5级和电流负载相同的情况下,文中提出的电荷泵相比现有电荷泵具有更高的输出电压和更小的电压纹波。     

精确实用的电压-频率转换电路

<正> 本文介绍的电压-频率转换电路,不仅是一种实用而精确的电路,而且还具有转换频率的上下限控制电路。它用于控制电机转速时,可以限制电机的最低转速和最高转速。从而有效地防止了电机的超高速和过低速的运行。该电路可以实现无级调速,且转换精度高,抗干扰性能强,测试简单。 该电路如图所示。以三极管U1和双向门IC12为核心的电路是转换频率设置电路。三极管U1是用来控制双向门IC12的。当从电阻R1输入一个低电平时,三极管U1截止,其集电极输出高电平,使双向门IC12导通,通过S按     

一个有利于消除电荷共享的新型电荷泵

为了消除电荷泵的电荷共享效应,通过在发生电荷共享的节点预置一个特定的电压,设计出了一个适用于频率合成器的新型电荷泵.在Chartered公司0.18 RF CMOS工艺条件下,HSPICE的仿真结果表明,这一新型电荷泵与传统的相比,很好地抑制了电荷共享效应,具有很低的输出纹波,在高性能频率合成器中具有良好的应用前景.     

电压转换电路的改进设计

某系统中应用XTR110电路，设计电压到电流的转换，但XTR110电路中输出电流出现错误，提出改进的输入参考电压的电路设计方法，并用改进后的电路实现原理电路设计所要求的电流输出。     

F／V及V／F转换电路的原理与应用

介绍AD650的结构及特点，详细讨论它的工作原理与典型应用电路的设计及调整。     

基于低压CMOS工艺的新型负电压型电荷泵电路

采用UMC 0.18 μm 1.8 V/3.3 V CMOS工艺设计并流片验证了一个应用于生医刺激器的新型负电压型电荷泵电路.介绍了几种典型的负电压型电荷泵电路,比较其优缺点,在此基础上设计了一个新型4级交叉耦合型负电压电荷泵.和现有的结构相比,该电路在启动过程和工作过程中都不存在过压问题,器件任意两端口之间的电压均小于电源电压VDD,同时降低了MOS器件衬底效应、反向漏电流对电荷泵效率的影响.电荷泵的电容采用MIM电容,升压电容为50 pF,输出电容为100 pF.芯片面积为2.3 mm×1.3 mm,测试结果表明负电压型电荷泵电路输出电压为-10.3 V,系统最高效率为56％.当输出电流为3.5 mA时,输出电容为100 pF时,纹波电压为150 mV.     

基于电荷泵的倍增/反向双输出电压转换设计与实现

为了解决目前基于电荷泵的开关电容电压转换芯片功能较为单一的问题,基于Dickson经典电荷泵结构,匹配四路双极型晶体管开关同时实现对输入电压的倍增输出以及倍增后的电压反向。四路二极管充作开关来使用,在降低开关器件导通电压的同时简化了开关电路,缩小了电路的尺寸,并降低了电路的功耗。基于国内某工艺线的40 V互补双极型工艺,设计并制作了带正/负两路输出的开关电容电荷泵电压转换器芯片电路。流片测试结果表明：当电源电压为4 V（负载电流为0 mA、+10 mA）、5 V（负载电流为±10 mA）、9 V（负载电流为+10 mA）、10 V（负载电流为-10 mA）以及11 V（空载）时,输出电压均满足设计指标。     

3V/5V标准单元混合使用的芯片设计

讨论了 0 .9μm标准单元正向设计流程中当电路中存在 5 V和 3 V两种电压时芯片的设计方法 ,包括网表产生与验证 ,版图设计 ,电压转换单元的加入原则。     

基于对偶逻辑的混合极性 RM 电路极性转换和优化方法

针对混合极性RM（Reed-Muller）电路逻辑综合中的极性转换和极性优化问题,提出了基于对偶逻辑的极性转换和极性优化方法。从理论上证明了所提出方法的正确性,并用实验验证了其有效性和可行性。所提出方法有助于将较成熟的MPRM （Mixed-Polarity RM ）极性转换和极性优化方法应用于MPDRM （Mixed-Polarity Dual form of RM ）。对15个基于XOR的MCNC电路进行逻辑综合然后映射到FPGA （Field Programmable Gate Array ）的实验结果表明,从平均结果来看,与逻辑综合工具Espresso以及ABC的结果相比,混合极性RM电路能够获得面积和延时的优势,并且MPDRM电路极性优化结果能够得到最为优化的FPGA实现。     

5V转换成-10V的简单电路

典型开关式电容器充电泵不需要电感器，因此容易设计．且能将正电压加倍及将正电压转换成一个等效负电压。但在某些应用中．只有正电源可用．且电源系统必须产生一个幅度比正电源电压幅度更大的负电压。图1所示电路可将其输入电压反相的同时将所得负电压加倍。     

Charge pump circuits: power consumption optimization - a summary

In this paper, an optimized strategy for designing charge pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35 /spl mu/m EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.     

Charge pump power-factor-correction dimming electronic ballast

A voltage-source charge pump power-factor correction (CPPFC) continuous dimming electronic ballast is proposed in this paper. The basic charge pump PFC principle is presented, and its unity power factor condition is then reviewed. Constant lamp power control and crest factor correction technique in dimming mode operation are then discussed. A continuous dimming controller with average lamp current control and duty-cycle modulation is developed so that the lamp is able to operate in constant power and low crest factor from 20% to 100% dimming level. The developed dimming electronic ballast has features of higher than 0.99 power factor, low crest factor, and low-DC-bus voltage     

Charge pump power-factor-correction technologies. II. Ballastapplications

For pt.I see ibid., vol.15, no.1, p.121-9 (2000). Charge pump power-factor-correction (CPPFC) converters using voltage-source (VS) CPPFC, current-source (CS) CPPFC, and continuous input current (CIC) CPPFC techniques are developed in this paper. Design considerations and the performance of the CPPFC electronic ballasts are discussed, analyzed, and evaluated. The experimental results show that 0.99 power factor and 10% total harmonic distortion (THD) can be achieved. It is shown that the CPPFC techniques are very attractive     

由-5V产生IA、3.3V的简单电路

图1所示的电路,利用脉冲频率调制(PFM)结构从-5V电源产生 3.3V输出,不需要任何外部变压器.当有一个稳定的-5V电源,并且不要求隔离时,这是一个非常实用的电路.     

Charge pump with perfect current matching characteristics inphase-locked loops

Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLL output signals. In particular, it reduces the locking range in wide range PLLs with a dual loop scheme. A new charge pump circuit with perfect current matching characteristics is proposed. By using an error amplifier and reference current sources, one can achieve a charge pump with good current matching characteristics. It shows nearly perfect current matching characteristics over the whole VCO input range, and the amount of the reference spur is <-75 dBc in the PLL output signal. The charge pump circuit is implemented in a 0.25 μm CMOS process     

Charge pump power-factor-correction technologies. I. Concept andprinciple

Charge pump power-factor-correction (CPPFC) technologies, including voltage-source (VS) CPPFC, current-source (CS) CPPFC, and continuous input current (CIC) CPPFC, are presented in this paper. The charge pump concept for achieving PFC and its unity power factor conditions are derived and analyzed, The developed CPPFC techniques use a capacitor to achieve PFC function     

Charge pump boosting technique for power noise immune high-speedPLL implementation

A phase-locked loop (PLL) with a charge pump boosting technique is described. The technique enables the voltage controlled oscillator circuit in the PLL to run faster than conventional circuits at low supply voltage. This design method is applicable to PLLs with low jitter, high-speed characteristics in environments with high supply noise     

Charge pump circuits with only capacitive loads: optimized design

Optimized strategies for designing charge pumps having only capacitive loads are presented. The design strategies developed are with minimum silicon area, which is equivalent to that with minimum rise time, and with minimum power consumption. The approach allows designers to define the number of stages that minimize silicon area (and minimize rise time) or maximize power efficiency for a given input and output voltage. The approaches were analytically developed and validated through simulations and experimental measurements on 0.18-/spl mu/m EEPROM CMOS technology. Moreover, a detail comparison between the two design strategies is also carried out.     

Charge pump design for high-voltage biasing applications in piezoelectric-based miniaturized robots

Fully autonomous piezoelectric-based miniaturized robots usually have a high-voltage biasing system that provides the required voltage levels to drive properly their piezoelectric actuators. In this paper a novel on-board biasing system based on the cascade connection of three full-custom charge pump ICs is presented. Simulated and experimental results show that the proposed biasing system is capable to obtain a regulated output voltage up to 20 V from a 3.3 V battery and deliver successfully up to 120 mW of power. Moreover, a novel approach in the steady-state analysis of the two-phase voltage doubler (which is the core of the designed charge pump IC) has been developed in order to have a tool capable to provide a full understanding of the steady-state voltage doubler’s behavior while at the same time accelerate and simplify the design process of such circuit. Simulated results show that the proposed mathematical model is more accurate than already developed models. The design of the charge pump IC has been implemented using a commercial 0.7 μm Bipolar-CMOS-DMOS (BCD) technology.