Modeling of SILC based on electron and hole tunneling. II.Steady-state

For pt. I see ibid., vol. 47, no. 6 (June 2000). A numerical model for the stationary stress-induced leakage current (SILC) is presented, accounting for both electron and hole tunneling. Detailed comparisons against experimental results on both n- and p-channel devices highlight that the steady-state SILC is due to positively charged centers, with an energy level located in correspondence of the silicon bandgap. Electron-hole recombination at these sites dominates normal trap-assisted tunneling at low oxide fields, and successfully accounts for recently observed hole steady-state leakage. The contribution from neutral traps seems instead marginal. Based on this new picture, the impact of the recombination process on the leakage properties of ultrathin gate is also discussed     

Experimental evidence of inelastic tunneling in stress-inducedleakage current

We propose a new experimental technique to study the transport properties of stress-induced leakage current (SILC). Based on the carrier separation measurement for p-channel MOSFETs, the quantum yield of impact ionization for electrons involved in the SILC process is evaluated directly from the change in the source and gate currents of p-MOSFETs before and after stressing. Since the relationship between the electron energy and the quantum yield is established for direct and FN tunneling currents, the electron energy of electrons involved in the SILC process can be determined from the quantum yield. The results reveal that the measured energy of electrons in the SILC process is lower roughly by 1.5 eV than the energy expected in the elastic tunneling process. Trap-assisted inelastic tunneling model is proposed as a conduction mechanism of SILC accompanied by energy relaxation. It is shown, through the evaluation of the substrate hole current in n-channel MOSFETs, that the contribution of trap-assisted valence electron tunneling, another possible mechanism to explain the energy relaxation, to SILC is small     

Hot hole stress induced leakage current (SILC) transient in tunneloxides

The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-Å oxide obeys a power law time dependence f^-n with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed     

On a universal parameter of intrinsic oxide breakdown based onanalysis of trap-generation characteristics

It is found, even at room temperature, that hole fluence to breakdown Q_p of wet oxides is not a constant value for different oxide fields, but has a strong stress-electric-field dependence. Based on the neutral trap-generation characteristics related to SILC, this oxide-breakdown behavior dependent on the stress-electric field is analyzed. A novel model is proposed in which oxide breakdown is triggered when the current level of steady-state SILC via electron tunneling between traps reaches a critical value. From the spatial distribution of traps, we have concentrated on the critical trap pair whose electron-tunneling probability has the smallest value in the middle of the SiO₂ films. To verify this model, the convoluted trap density which is related to the electron-tunneling probability between the critical trap pair is investigated. As a result, it is found that this convoluted trap density remains constant regardless of stress-electric field and oxide thickness. This means that this convoluted trap density is a universal parameter for oxide breakdown     

A model of the stress induced leakage current in gate oxides

A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress     

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

The carrier conduction and the degradation mechanism in n⁺gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO_X (Hf: 60 at.%, Al: 40 at.%)/SiO₂ dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO₂ layer (IL) thickness increases in a fixed high-k layer thickness (T_high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO₂/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of T_high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n⁺poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n⁺poly-Si gate. Both the defect generation rate and the defect size in the HfAlO_X/SiO₂ stacks are large compared with those in SiO₂. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO₂ could be related to a larger dielectric constant of the high-k layer.     

A new I-V model for stress-induced leakage current includinginelastic tunneling

A new I-V model to quantitatively represent stress-induced leakage current (SILC) is presented and compared with the experimental I-V characteristics. The trap-assisted tunneling model is modified so as to include the energy relaxation of tunneling electrons, which has been experimentally verified by applying the carrier separation technique to MOSFETs with the SILC component. The energy relaxation is treated in the new model as the change in the energy level of traps before and after the capture of electrons during two-step tunneling. It is demonstrated that this model successfully represents the experimental I-V characteristics of the SILC component and, particularly, the low apparent barrier height in the Fowler-Nordheim (FN) plot of the SILC component. The calculated low barrier height is attributed to the dominance of direct tunneling mechanism on both tunneling into traps and out of traps. The impact of the energy relaxation during tunneling, used in the present model, on the I-V characteristics is discussed in terms of the trap distribution inside the gate oxide, compared with conventional elastic tunneling model     

The charging and discharging of high-voltage stress-generated trapsin thin silicon oxide

Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide     

Analysis of current flow in polycrystalline TFTs

A model for predicting the change of currents at the surface of polycrystalline materials for both ohmic and blocking contacts is developed. The model includes electron/hole traps within grain boundaries that are comparable in thickness to that of the dielectric on the surface of the polycrystalline semiconductor. The grains and their interfaces with the dielectric are assumed to be trap free. Account is also taken of the reducing carrier Debye Length as the surface carrier concentration is increased, from its intrinsic value, by the field effect. The net surface conductance is obtained by integrating the carrier density across the surface region through to the back of the material. Four regimes are identified: quasi-drift and quasi-diffusion for the high and low current regimes when there is a good supply of carriers and generation and quasi-diffusion when there is a limited supply of carriers. The analytical relationships are found to give satisfactory agreement with results for the temperature and field dependence of surface conductance in polycrystalline silicon in these regimes. The dependence of surface conductance on field effect voltage is found, at lower currents, to be a means of determining the energy distribution of electron/hole traps.     

The SILC study by PDO method

Stress induced leakage current (SILC) has been discussed for a long time by many researchers. The oxide traps are believed to be the cause of SILC, but characterization of these traps is still not clear. In this paper, we demonstrate that the SILC related oxide traps can be distinguished into two kinds with different characterization parameter by PDO method. Linear fitting also shows that double oxide trap model is better than single oxide trap model.     

New results on electron injection, hole injection, and trapping in MONOS nonvolatile memory devices

Charge injection and trapping in silicon nitride layers are studied with the three-terminal metal-oxide-nitride-oxide-semiconductor (MONOS) gated-diode structure. A new experimental technique based on the linear voltage ramp is developed which measures electron and hole currents separately in the semiconductor during the actual charge injection (nonsteady-state measurement as opposed to the steady-state method) across the tunneling oxide. In addition, the technique measures the flat-band voltage shift and minimizes the back tunneling of the injected charge (a problem with the pulse measurement). The blocking oxide between the gate electrode and the nitride layer prevents any injection from the gate electrode. The main conclusion from these studies is that the semiconductor injects electrons and holes into the nitride layer for positive and negative polarities of the gate bias, respectively. This result is in sharp contrast with the existing interpretations based on a single-carrier type. It is speculated that the recombination of electrons and holes takes place in the nitride layer via an "amphoteric" trap. At small levels of charge injection, centroids of the trapped charge (measured from the tunneling oxide-nitride interface) for both electron and hole injection conditions are found to be located at 75-80 Å at room temperature and 15-20 Å at 100 K.     

Numerical confirmation of inelastic trap-assisted tunneling (ITAT)as SILC mechanism

This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density N_t, and the trap energy level E_t. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are thoroughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build N _t explicitly as a function of the stress electron fluence. Then the overall tunneling probability is calculated, with which a best fitting to SILC I-V furnishes τ of 4.0×10^-13 s and E_t of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well     

Characterization of oxide trap energy by analysis of the SILC roll-off regime in flash memories

We present a novel experimental technique to identify the energy of traps responsible for the stress-induced leakage current (SILC) in Flash memories, based on a standard gate-stress analysis with a drain bias used to accelerate channel electrons. From the study of the rolloff in SILC characteristics, we provide evidence for the existence of high-energy traps in the silicon dioxide, located at energies above the silicon conduction band minimum. The new technique is able to characterize the position of defects along the channel and the electron effective temperature at the SILC spot, allowing to extract the dependence of channel electron temperature on the distance from the drain.     

Two types of neutral electron traps generated in the gate silicon dioxide

Electron trap generation in the gate oxide is a severe problem for the reliability of MOS devices, since it can cause stress-induced leakage current (SILC) and eventually lead to oxide breakdown. Although much effort has recently been made to understand the mechanism for the trap generation, the properties of the generated traps have received relatively less attention. The objective of this paper is to present unambiguous results, showing that two different types of neutral electron traps can be created by the same stress and to compare the properties of these two types of traps. Differences have been found in terms of their generation kinetics, trap filling, detrapping, and refilling after detrapping. The results also indicate that the energy levels of these two types of traps are different.     

Bulk traps in silicon-on-sapphire by conductance DLTS

A new deep-level transient spectroscopy (DLTS) technique has been developed for the characterization of deep-level imperfection centers in silicon-on-sapphire (SOS) epitaxial layers, and is based on the use of conductance transients on MOSFET's. Both the distribution of trap levels with energy in the bandgap of silicon and the spatial distribution of levels in the epitaxial film have been obtained. This complete characterization of trapping levels allows process techniques to be developed to control and reduce their concentrations to acceptable levels in SOS technology.     

On the correlation between SILC and hole fluence throughout the oxide

Stress-induced leakage current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a reliable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime[1]. The physical origin and mechanisms of SILC have not yet been clearly understood and several points open to discussion remain. In this work the role of oxide hole fluence in producing the SILC is discussed. An universal power law of SILC generation kinetics is proposed versus the hole fluence throughout the oxide. The experimental results are theoretically validated by modeling the measured quantum-yield by the contributions of both anode hole injection and electron valence band injection mechanisms.     

Simplified quantitative stress-induced leakage current (SILC) model for MOS devices

A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced the time of numerical calculations of SILC to 17% of the standard method while maintaining a high accuracy of the results. We also confirmed that the SILC component must not be neglected when calculating the gate current in modern devices, especially at low fields. Our simplified model helped us to investigate the dependence of SILC on the oxide field and the oxide thickness. We also shed some light on the reasons that cause the peak in the SILC–oxide thickness relation.     

Role of positive trapped charge in stress-induced leakage current for flash EEPROM devices

The transient behavior of hot hole (HH) stress-induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence t/sup -n/ with the power factor n about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time- and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a flash EEPROM cell is derived. Finally, the dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100 /spl Aring/ to 53 /spl Aring/, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT).     

Trap generation and breakdown processes in very thin gate oxides

Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented.