Influences of buried-oxide interface on inversion-layer mobility inultra-thin SOI MOSFETs

This paper reports on a study of the inversion-layer mobility in n-channel Si MOSFETs fabricated on a silicon-on-insulator (SOI) substrate. In order to make clear the influences of the buried-oxide interface on the inversion-layer mobility in ultra-thin film SOI transistors, SOI wafers of different quality at the buried-oxide interface were prepared, and the mobility behaviors were compared quantitatively. The transistors with a relatively thick SOI film exhibited the universal relationship between the effective mobility and the effective normal field, regardless of the buried-oxide interface quality. It was found, however, that Coulomb scattering due to charged centers at the backside interface between SOI films and buried oxides has great influence on the effective mobility in the thin SOI thickness region, depending on the buried-oxide interface quality. This means that Coulomb scattering due to charged centers at the buried-oxide interface can degrade the mobility with decreasing SOI thickness, unless the SOI wafer quality at the buried-oxide interface is controlled carefully     

Temperature dependence of hot-carrier-induced degradation in 0.1μm SOI nMOSFETs with thin oxide

This letter investigates hot-carrier-induced degradation on 0.1 μm partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect     

SOI NLIGBT热载流子效应研究

SOI NLIGBT中热载流子效应分别通过直流电压的应力测试、TCAD仿真和电荷泵测试三种方法进行了研究。其中,不同直流电压应力条件下测得的衬底电流Isub和导通电阻Ron用来评估因热载流子效应引起的器件退化程度。为了进行理论分析,对器件内部的电场强度和碰撞离化率也进行了仿真。测试得到的电荷泵电流直接验证了器件表面的损伤程度。最后讨论了SOI LIGBT在不同栅压条件下的退化机制。     

Investigation on hot-carrier-induced degradation of SOI NLIGBT

The hot-carrier-induced (HCI) degradations of silicon-on-insulator (SOI) lateral insulated gate N-type bipolar transistor (NLIGBT) are investigated in detail by DC voltage stress experiment, TCAD simulation and charge pumping test. The substrate current I_sub and on-state resistance Ron at different voltage stress conditions are measured to assess the HCI effect on device performance. The electric field and impact ionization rate are simulated to assist in providing better physical insights. And charge pumping current is measured to determinate the front-gate interface states density directly. The degradation mechanisms under different gate voltage stress conditions are then presented and summarized.     

Hot carrier-induced SOI MOSFET degradation under AC stressconditions

The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested     

Short-channel single-gate SOI MOSFET model

The authors derive an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers. Their model is valid for both long- and short-channel SOI MOSFETs and demonstrates the dependence of short-channel effects on the device parameters of channel-doping concentration, gate oxide, SOI, and buried-oxide thickness. It reproduces the numerical data for sub-0.1-/spl mu/m gate-length devices better than previous models.     

A model for analyzing the interface properties of asemiconductor-insulator-semiconductor structure. I. Capacitance andconductance techniques

A model is presented for analyzing the interface properties of a semiconductor-insulator-semiconductor (SIS) capacitor structure. By introducing a coupling factor, conventional metal-oxide-semiconductor (MOS) capacitor theory is extended to analyze the interface properties of the film/buried-oxide/substrate interfaces of a silicon-on-insulator (SOI) material. This model was used to determine parameters such as doping concentration, buried oxide thickness, fixed oxide charge, and interface trap density from the SIMOX (separation by implantation of oxygen) based SIS capacitors     

The effect of post-oxygen-implant annealing temperature on the channel mobilities of CMOS devices in oxygen-implanted silicon-on-insulator structures

The effects of post-oxygen-implant annealing temperature on the characteristics of MOSFET's in oxygen-implanted silicon-on-insulator (SOI) substrates are studied. The results show significant improvements in the electron and hole mobilities near the silicon/buried-oxide interface and in the electron mobility of the front-gate n-channel transistors in SOI substrates with higher post-oxygen-implant annealing temperature. The improvements in the transistor characteristics hence are attributed to the annihilation of oxygen precipitates and the reduction of defect density in the residual silicon film. By comparing the ring oscillators fabricated in SOI substrates annealed at 1150°C and 1250°C after oxygen implantation, a speed improvement of 15 percent is observed in substrates annealed at higher temperature.     

An efficient method for characterizing time-evolutional interfacestate and its correlation with the device degradation in LDD n-MOSFETs

A new characterization method is proposed to study the relationship between the hot-carrier-induced interface state N_it (x) and the device drain current degradation of submicron LDD n-MOSFETs. In this method, by making use of the conventional charge pumping measurement in combination with the power-law dependence of interface damages on stress time, the spatial distribution N_it(x) and the effective damaged length L_dam can be easily extracted. The time evolution of the interface state generation and its correlation with the device degradation can then be well explained. It is worthwhile to note that this newly developed method requires no repetitive charge pumping measurements, and hence avoids he likely imposition of re-stress on tested devices. By combining the characterized L_dam and N_it quantitatively, the results show that the damage at L_dam and V_GS≈V _DS/2 is most highly localized among various stress biases, which can explain why the generated interface states will dominate the device drain current degradation at this bias after long-term operating conditions     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

New hot-carrier-degradation mode in thin-film SOI nMOSFET's

A new hot-carrier degradation mode peculiar to MOSFET's fabricated on thin-film SOI is described. This degradation mode, which occurs in nMOSFET's more easily than in pMOSFET's, is due to suppression of parasitic bipolar action caused by recombination of excess carriers through hot-carrier-induced front interface-traps. Threshold voltage is significantly shifted by this phenomenon. The reliability lifetime defined by threshold voltage shift and drain current degradation is also discussed, considering the new degradation mode     

Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 /spl mu/m CMOSFET with 2-nm thin gate oxide

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 /spl mu/m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 /spl mu/m FB-SOI pMOSFET is similar to that of the 0.1 /spl mu/m BC-SOI pMOSFET.     

Hot-carrier-induced degradation of drain current hysteresis and transients in thin gate oxide floating body partially depleted SOI nMOSFETs

The impact of hot-carrier degradation on drain current (I_D) hysteresis and switch-off I_D transients of thin gate oxide floating body PD SOI nMOSFETs is analyzed. An extended characterization of these floating body effects (FBEs) is carried out for a wide range of transistor geometries and bias conditions. The results show a link between the hot-carrier-induced damage of the front channel and the reduction of the FBEs. This is further supported by unbiased thermal annealing experiments, which are found to give rise to a partial recovery of the hot-carrier induced damage and FBEs.     

Buried-oxide charge trapping induced performance degradation infully-depleted ultra-thin SOI p-MOSFET's

The buried-oxide charge trapping induced performance degradation was studied in fully-depleted, ultra-thin SOI p-MOSFET's fabricated on SIMOX wafers. The trapped holes were introduced by X-ray irradiation, and the trapped electrons were introduced by hot hole impact ionization. Subthreshold slope and current drive degradations were observed due to hole-trapping in the buried oxide, via electrostatic coupling between the front and back interfaces. Simulation results showed much reduced performance degradation in SOI p-MOSFET's using thin buried oxides. A minimal interaction of front-channel hot-carrier and radiation effects on the buried oxide degradation, was observed in 0.3-μm channel length transistors     

Modeling and simulation of hot-carrier-induced device degradationin MOS circuits

The physical models and an integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model includes both fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET’S

The hot-carrier-induced oxide regions in the front and back interfaces are systematic-cally studied for partially depleted SOI MOSFET‘s .The gate oxide properties are investigated for channel hot-carrier effects.The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection,i.e.the maximum gate current, maximum substrate current and parasitic bipolaf transistor action.Experiments show that PMOSFET‘s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET‘s degradation is caused by hot holes.This paper reports for the first time that the electric characteristics of NMOSFET‘s and PMOSFET‘s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided.     

Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation

This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability.     

50-Å gate-Oxide MOSFET's at 77 K

While hot-carrier-induced degradation is aggravated at cryogenic temperature, a very thin gate-oxide (52-Å) device can still tolerate a 3-V power-supply voltage at 77 K. Hot-carrier-induced degradation may not be the limiting factor in choosing the power-supply voltage and special drain structures may be necessary for very thin gate MOSFET's even at 77 K. However, mobility reduction at high VGis more severe both at lower temperatures and for thinner oxides. Electron mobility appears to be oxide-thickness-dependent at 77 K. The dependence of the electron mobility on the normal field is so strong that it results in unusual I-V characteristics such as negative transconductance at 77 K for an oxide field above 3 MV/cm. The I--V characteristics have been modeled with a mobility dependence on VGSof the form µn ∞ (1 + η(VGS- Vt/Tox)²+ (E/Ec))^-1for 52-Å devices.     

Hot-carrier effects and reliable lifetime prediction in deepsubmicron N- and P-channel SOI MOSFETs

Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 μm down to 0.1 μm. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (V_g≈V_d ), maximum substrate current (V_g≈V_d/2) and parasitic bipolar transistor (PBT) action (V_g≈0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range     

SOI thermal impedance extraction methodology and its significancefor circuit simulation

The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (R_th) and thermal capacitance (C_th) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits