Unified quasi-static MOSFET capacitance model

An accurate calculation of MOSFET capacitance-voltage (C V) characteristics has to account for the bulk charge which is affected by nonuniform doping profiles and short-channel effects. In an approach based on the unified charge control model (UCCM), the voltage dependencies of the bulk charge are related to the standard parameters of the body plots which are routinely measured during MOSFET characterization. The results of the C-V calculations based on this model are in good agreement with experimental data and calculations based on the standard BSIM model. Compared to the BSIM simulations, the present model more accurately describes capacitances related to the bulk charge and the device subthreshold behavior, and it is suitable for incorporation into circuit simulators     

An analytical model for the threshold voltage of a narrow-width MOSFET

A closed form analytical expression is derived to predict the threshold voltage of a narrow-width MOSFET. The present calculation utilizes the Fourier transform technique to analyze the voltage over the width cross section of the basic MOS device structure. No fitting parameter with experimental data is necessary because the fringe electric field is calculated directly from the relevant physical parameters to deduce the threshold voltage. The dependence of threshold voltage on channel width and substrate bias thus obtained is in reasonable agreement with experimental and numerical results. The effects of field doping and field oxide thickness on the threshold voltage are also taken into consideration. A comparison is made of the present analytical expression for threshold voltage with that, based on an adjustable weighting factor, of earlier analytical models.     

A one-dimensional analytical model for the dual-gate-controlledthin-film SOI MOSFET

A one-dimensional analytical model for dual-gate-controlled SOI MOSFETs is presented and applied to a stacked p-channel MOSFET fabricated by epitaxial lateral overgrowth (ELO). The authors found and modeled a nonlinear dependence of front-gate threshold voltage on back-gate voltage if threshold is defined by a constant current instead of a constant silicon-surface potential. It is demonstrated by comparison of subthreshold slopes that surface potentials are not pinned to the onset of strong inversion or accumulation. Accurate one-dimensional modeling is a necessity for device characterization and a precondition for general SOI models for circuit simulation     

An analytical CMOS inverter delay model including channel-lengthmodulations

An analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced. This model is based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region. Calculations of the rise, fall, and delay times show good agreement with SPICE MOS level three simulations     

An analytical expression for MOSFET gate leakage current

Integral expressions for the gate leakage current in a MOSFET are derived on the basis of Schottky emission across the gate insulator and on the internal self-heating due to device power dissipation. Computer evaluation of these integrals yields gate leakage current curves that exhibit the same characteristics observed experimentally.     

An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET

In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L₁/L₂ ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement.     

MOSFET substrate current model including energy transport

A new MOSFET substrate current model, incorporating energy transport, is proposed. It was found that a non-steady-state electron transport effect and two effects attributed to electron pressure are essential to calculate the substrate current characteristics accurately. The predictions from the present model compare favorably with the experimental data for MOSFET's with effective channel length down to 0.45 µm.     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.     

An accurate method of determining MOSFET gate overlap capacitance

A new method to determine gate overlap capacitance from measurements in the inversion regime of MOSFET operation is reported. Measured overlap capacitance, for submicron LDD devices, using the new method is compared with the conventional method of determining overlap capacitance from accumulation and with the reverse-biased source/drain junction method. Since transistors are rarely in accumulation during the normal operation of digital circuits, the traditional method of overlap capacitance extraction in accumulation is inappropriate. Many digital circuits operate primarily in inversion; using our new method these circuits can be modeled more accurately.     

The lumped-charge power MOSFET model, including parameterextraction

A fundamentally new, physically-based power MOSFET model features continuous and accurate curves for all three interelectrode capacitances. The model equations are derived from the charge stored on two internal nodes and the three external terminals. A straightforward parameter extraction technique uses the standard gate-charge plot or process data and is matched with interelectrode capacitance measurements. Simulations are in excellent agreement with measurements. The model is used to design a snubber for a flyback converter     

An analytical expression for the threshold voltage of a small geometry MOSFET

A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close.     

An improved MOSFET model for circuit simulation

Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model     

An analytical fully-depleted SOI MOSFET model considering theeffects of self-heating and source/drain resistance

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries     

A large-signal SOI MOSFET model including dynamic self-heatingbased on small-signal model parameters

A new technique for a large-signal SOI MOSFET model with self-heating is proposed, based on thermal and electrical parameters extracted by fitting a small-signal model to measured s-parameters. A thermal derivative approach is developed to calculate the thermal resistance when the isothermal dc drain conductance is extracted from small-signal fitting. The thermal resistance is used to convert the measured dc current-voltage (I-V) characteristics containing the self-heating effects to the isothermal I-V characteristics needed for the large-signal model. Large-signal pulse and sinusoidal input signals are used to verify the model by measurement, and shown to reproduce the observed large-signal behavior of the devices with great accuracy, especially when two or more thermal time constants are used     

MOSFET capacitance and conductance in the saturation regime

The relationship between capacitance and conductance of a MOSFET is examined in the region where velocity saturation dominates. In this domain it is shown that charge on the drain terminal (physically distinct from that in the channel) most be considered in order to keep the model from predicting the unphysical result that C_gd is negative. It is also shown that, under the same assumptions, g_m<C_gg/τ where g _m is the transconductance, τ is the transit time, and C_gg is the gate capacitance     

An accurate photonic capacitance model for GaAs MESFETs

A new set of pseudoempirical equations is presented in order to simulate the optical and bias dependencies of GaAs MESFET junction capacitances, which is valid for the whole I-V plane. The variations induced in the small-signal equivalent circuit by the optical illumination are extracted from on-wafer scattering parameter measurements. New linear and quasi-logarithmic variations versus the incident optical power are shown for gate-drain and gate-source (Cgd and Cgs) capacitances. Furthermore, experimental results are in very good agreement with the simulated values for a wide range of optical power and bias conditions. Large signal MESFET models show a better fit with measured S-parameters than those previously published, leading to a greater degree of confidence in the design of photonic monolithic microwave integrated circuits     

An efficient CAD-oriented large-signal MOSFET model

An efficient computer-aided-design-oriented large-signal microwave model for silicon MOSFETs is presented based on the well-founded small-signal equivalent circuit including self-heating effect and charge conservation condition. The proposed new single continuously differentiable empirical equations for drain current and gate capacitance are simple and quite accurate. The model parameters in the equations are constructed in such a way that they can be easily and straightforwardly extracted from measured data. The temperature effect is predicted by simply adopting the linear temperature-dependent model parameters for threshold voltage, saturation current, capacitance, and series resistances. The presented model is a good compromise between the simplicity of numerical calculations and the accuracy of final results that is desired by circuit designers in nonlinear circuit simulation     

Comparison of quasi-static and non-quasi-static capacitance models for the four-terminal MOSFET

Analytic comparison of quasi-static and non-quasi-static capacitance models is performed for the four-terminal MOSFET with the bulk charge effect included under all operating regimes (weak, moderate, and strong inversion). It is shown that, with the use of a linearized bulk charge density, the Ward quasi-static charge-based approach [2] is equivalent to the non-quasi-static solution [5] in terms of the capacitances calculated at low frequencies. Such a mathematical link between the two approaches may be crucial toward developing high-frequency models for transient analysis.     

一种VOD系统的分析模型

对全连网络的分布式视频点播系统进行了性能分析,提出了一种VOD系统的分析模型,可以利用这一模型计算视频请球发生拥塞的概率以及网络的带宽要求,同时还可以得到在通信和存储费用两者之间的一个折衷方案。