共查询到20条相似文献,搜索用时 15 毫秒
1.
《Microelectronics Reliability》2015,55(1):38-41
An analytical model of avalanche breakdown for double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented. First of all, the effective mobility (μeff) model is defined to replace the constant mobility model. The channel length modulation (CLM) effect is modeled by solving the Poisson’s equation. The avalanche multiplication factor (M) is calculated using the length of saturation region (ΔL). It is shown that the avalanche breakdown characteristics calculated from the analytical model agree well with commercially available 2D numerical simulation results. Based on the results, the reliability of the DG MOSFET can be estimated using the proposed analytical model. 相似文献
2.
An accurate calculation of MOSFET capacitance-voltage (C V ) characteristics has to account for the bulk charge which is affected by nonuniform doping profiles and short-channel effects. In an approach based on the unified charge control model (UCCM), the voltage dependencies of the bulk charge are related to the standard parameters of the body plots which are routinely measured during MOSFET characterization. The results of the C -V calculations based on this model are in good agreement with experimental data and calculations based on the standard BSIM model. Compared to the BSIM simulations, the present model more accurately describes capacitances related to the bulk charge and the device subthreshold behavior, and it is suitable for incorporation into circuit simulators 相似文献
3.
《Electron Devices, IEEE Transactions on》1984,31(12):1814-1823
A closed form analytical expression is derived to predict the threshold voltage of a narrow-width MOSFET. The present calculation utilizes the Fourier transform technique to analyze the voltage over the width cross section of the basic MOS device structure. No fitting parameter with experimental data is necessary because the fringe electric field is calculated directly from the relevant physical parameters to deduce the threshold voltage. The dependence of threshold voltage on channel width and substrate bias thus obtained is in reasonable agreement with experimental and numerical results. The effects of field doping and field oxide thickness on the threshold voltage are also taken into consideration. A comparison is made of the present analytical expression for threshold voltage with that, based on an adjustable weighting factor, of earlier analytical models. 相似文献
4.
A one-dimensional analytical model for dual-gate-controlled SOI MOSFETs is presented and applied to a stacked p-channel MOSFET fabricated by epitaxial lateral overgrowth (ELO). The authors found and modeled a nonlinear dependence of front-gate threshold voltage on back-gate voltage if threshold is defined by a constant current instead of a constant silicon-surface potential. It is demonstrated by comparison of subthreshold slopes that surface potentials are not pinned to the onset of strong inversion or accumulation. Accurate one-dimensional modeling is a necessity for device characterization and a precondition for general SOI models for circuit simulation 相似文献
5.
Hwang-Cherng Chow Wu-Shiung Feng 《Solid-State Circuits, IEEE Journal of》1992,27(9):1303-1306
An analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced. This model is based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region. Calculations of the rise, fall, and delay times show good agreement with SPICE MOS level three simulations 相似文献
6.
《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1973,61(10):1509-1510
Integral expressions for the gate leakage current in a MOSFET are derived on the basis of Schottky emission across the gate insulator and on the internal self-heating due to device power dissipation. Computer evaluation of these integrals yields gate leakage current curves that exhibit the same characteristics observed experimentally. 相似文献
7.
In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L1/L2 ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement. 相似文献
8.
《Solid-state electronics》2006,50(7-8):1276-1282
This paper describes an explicit analytical charge-based model of an undoped independent double gate (DG) MOSFET. This model is based on Poisson equation resolution and field continuity equations. Without any fitting parameter or charge sheet approximation, it provides explicit analytical expressions of both inversion charge and drain current considering long undoped transistor. Consequently, this is a fully analytical and predictive model allowing describing planar DG MOSFET as well as FinFET structures. The validity of this model is demonstrated by comparison with Atlas simulations. 相似文献
9.
In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model. 相似文献
10.
《Electron Device Letters, IEEE》1987,8(5):214-216
A new MOSFET substrate current model, incorporating energy transport, is proposed. It was found that a non-steady-state electron transport effect and two effects attributed to electron pressure are essential to calculate the substrate current characteristics accurately. The predictions from the present model compare favorably with the experimental data for MOSFET's with effective channel length down to 0.45 µm. 相似文献
11.
A new method to determine gate overlap capacitance from measurements in the inversion regime of MOSFET operation is reported. Measured overlap capacitance, for submicron LDD devices, using the new method is compared with the conventional method of determining overlap capacitance from accumulation and with the reverse-biased source/drain junction method. Since transistors are rarely in accumulation during the normal operation of digital circuits, the traditional method of overlap capacitance extraction in accumulation is inappropriate. Many digital circuits operate primarily in inversion; using our new method these circuits can be modeled more accurately. 相似文献
12.
A fundamentally new, physically-based power MOSFET model features continuous and accurate curves for all three interelectrode capacitances. The model equations are derived from the charge stored on two internal nodes and the three external terminals. A straightforward parameter extraction technique uses the standard gate-charge plot or process data and is matched with interelectrode capacitance measurements. Simulations are in excellent agreement with measurements. The model is used to design a snubber for a flyback converter 相似文献
13.
L.A. Akers 《Solid-state electronics》1981,24(7):621-627
A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close. 相似文献
14.
An improved MOSFET model for circuit simulation 总被引:3,自引:0,他引:3
Joardar K. Gullapalli K.K. McAndrew C.C. Burnham M.E. Wild A. 《Electron Devices, IEEE Transactions on》1998,45(1):134-148
Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model 相似文献
15.
Man-Chun Hu Sheng-Lyang Jang 《Electron Devices, IEEE Transactions on》1998,45(4):797-801
In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries 相似文献
16.
Roobik Gharabagi 《International Journal of Electronics》2013,100(2):129-136
An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement. 相似文献
17.
A large-signal SOI MOSFET model including dynamic self-heatingbased on small-signal model parameters
A new technique for a large-signal SOI MOSFET model with self-heating is proposed, based on thermal and electrical parameters extracted by fitting a small-signal model to measured s-parameters. A thermal derivative approach is developed to calculate the thermal resistance when the isothermal dc drain conductance is extracted from small-signal fitting. The thermal resistance is used to convert the measured dc current-voltage (I-V) characteristics containing the self-heating effects to the isothermal I-V characteristics needed for the large-signal model. Large-signal pulse and sinusoidal input signals are used to verify the model by measurement, and shown to reproduce the observed large-signal behavior of the devices with great accuracy, especially when two or more thermal time constants are used 相似文献
18.
The relationship between capacitance and conductance of a MOSFET is examined in the region where velocity saturation dominates. In this domain it is shown that charge on the drain terminal (physically distinct from that in the channel) most be considered in order to keep the model from predicting the unphysical result that C gd is negative. It is also shown that, under the same assumptions, g m<C gg/τ where g m is the transconductance, τ is the transit time, and C gg is the gate capacitance 相似文献
19.
Hasler P. Dugger J. 《IEEE transactions on circuits and systems. I, Regular papers》2005,52(5):834-845
We present an improved analog floating-gate pFET synapse that implements a supervised learning algorithm similar to the least mean square (LMS) learning rule. Weight decay plays a key role in several learning rules; this floating-gate synapse exhibits this behavior. We examine implications of the weight decay appearing in the correlation learning rule realized in the floating-gate synapse and provide experimental data characterizing the synapse and its performance in one-input and two-input LMS networks. Analog floating-gate synapses will enable larger-scale, on-chip learning networks than previously possible. 相似文献
20.