基于USRP的DVB-T接收机实现北大核心

为提高地面数字电视广播(DVB-T)接收机的实现灵活性,基于由通用软件无线电外设(Universal Software Radio Peripheral,USRP)和通用计算机组成的软件无线电平台,实现DVB-T接收机。接收机以USRP作为射频前端,在通用计算机中完成全部基带信号处理、视频解码与显示等。测试结果表明,接收机可实现对DVB-T信号的接收,为接收机算法开发、验证与评估提供了更为灵活的方法。     

DVB-T2接收机的算法实现与验证

DVB-T2是欧洲开发的新一代地面数字电视广播标准。为验证DVB-T2接收机算法在实际环境中的可行性,采用由个人计算机和通用软件无线电外设(Universal Software Radio Peripheral,USRP)搭建的软件无线电平台实现了DVB-T2接收机算法。该实现在计算机中完成全部基带信号处理与后续视频解码和显示等,算法验证灵活方便。实验结果表明,所实现的接收机算法可对DVB-T2信号正确接收,证明了接收机相关算法在实际环境中的可行性。     

基于USRP的中继系统的实现

基于通用软件无线电外设(Universal Software Radio Peripheral,USRP)和通用计算机组成的软件无线电平台,在基于DVB-T标准的无线多媒体传输系统中设计实现数字基带放大转发(Amplify-and-Forward,AF)系统和译码转发(Decode-and-Forward,DF)系统,并实现了动态参数配置和中继信号可视化。实现的中继系统具有很大的灵活性和可扩展性。实际测试结果表明,所设计的AF和DF中继系统可实现信号中继转发,有效扩大信号的覆盖范围,提高数据传输可靠性。     

基于LabVIEW和USRP的实时无线电频谱Web发布系统研究

利用USRP和LabVIEW对实时无线电信号进行处理,实现了基于网页的实时无线电频谱发布。     

基于USRP的L-DACS1前向链路设计与实现

L-band Digital Aeronautical Communications System 1(L-DACS1)是一种基于正交频分复用传输技术的宽带航空通信系统.依据L-DACS1系统规范,在USRP N210软件无线电平台设计实现了L-DACS1前向链路发射机与接收机,并在实验室环境下开展了前向链路传输试验....     

一种短波虚拟接收机的设计与实现

根据虚拟无线电技术原理设计了一种短波虚拟接收机,采用了短波宽带接收机和通用服务器实现了对短波信号的接收采集和数字化处理,通过数字信道化实现短波数字信号的窄带抽取和滤波,进而完成窄带信号的识别和解调。给出了短波虚拟接收机应用实例,并与传统接收机进行了对比测试,结果表明短波虚拟接收机与传统短波窄带接收机相比具有明显优势。     

基于软件无线电的天线阵方向图测量

本文设计了一种基于软件无线电的天线阵方向图测量实验。在1.5GHz频段下,手动搭建了一个以单极天线为单元的4元天线阵,并使用两台软件无线电设备USRP 2920分别连接单极天线和天线阵列以作为发射机和接收机。实验将发射机围绕接收机作圆周运动,记录发射天线所在方位角与接收信号的幅值强弱,在极坐标系内即可绘制出天线阵列在水平面内的实测方向图。本实验的测试结果与计算结果基本一致。     

综合化通信、导航、敌我识别系统(ICNIA)的通用接收机

研制这种通用接收机,是为了满足90年代战术飞机的综合化通信、导航、敌我识别系统(ICNIA)的需要.ITT公司研制的这种通用接收机具有很宽的可编程的调谐范围(2MHz～2GHz),这是ICNIA大多数信号所在的频段.通用接收机的性能比得上或超过了被ICNIA取代的离散无线电设备的性能.     

基于USRP平台的高灵敏度GNSS接收机算法研究

全球卫星导航系统正在不断发展,卫星接收机性能直接影响着导航定位的精确度。针对传统硬件接受机算法固定,灵活性不足的问题,文中进行了基于USRP(Universal Software Radio Peripheral)平台的全球卫星导航系统接收机研究。通过USRP平台对卫星信号进行中频采样及模数转换,然后在MATLAB软件中实现信号的捕获、跟踪和定位。针对微弱信号难以捕获的问题,在捕获算法中进行了信号的叠加操作,改进捕获判定方式,优化了傅里叶细化频率的方法。由于USRP无法产生整数倍码率的采样频率,导致相位误差产生进而影响伪距估计,所以对伪距估计算法进行了优化以提高定位精度。通过卫星定位实验对接收机性能进行验证,MATLAB中的实验结果表明,接受机灵敏度得以提高,定位精度满足要求。     

基于GNU Radio和USRP2的未知信号检测

运用开源软件无线电(GNU's Not Unix Radio,GNU Radio)技术和与之配套的通用软件无线电外设(TheSecond-generation Universal Software Radio Peripheral,USRP2),设计出了未知无线电信号自动检测系统。系统采用能量检测法,能够快速识别一定频段内未知无线电信号,并记录其带宽、中心频率和起止时间,同时存储相应的同相正交(Inphaseand Quadrature,IQ)数据,为后续载频的精确估计提供必要的参数。在实际测试中发现,该系统检测速度快、准确率高,对未知强信号检测具有一定的可靠性和实用性。     

A single-stage operational amplifier with enhanced transconductance and slew rate for switched-capacitor circuits

The DVB-T2 standard for digital terrestrial broadcasting supports the use of quadrature amplitude modulation constellations where the constellation points are rotated in the I–Q plane. This combined with a cyclic delay of the Q component provides improved performance in some fading channels. The complexity of the optimal demapping process for rotated constellations is however significantly higher than for non-rotated constellations. This makes the DVB-T2 demapper one of the most computationally complex parts of a receiver. In this article, we examine possible simplifications of the demapping process suitable for implementation on a general purpose computer containing a modern graphics processing unit (GPU). Furthermore, we measure the performance in terms of throughput, as well as accuracy, of the implemented algorithms. The implementations are designed to interface efficiently to a previously implemented real-time capable GPU-based low-density parity-check channel decoder.     

Complexity analysis of software defined DVB-T2 physical layer

The second generation terrestrial TV broadcasting standard from the digital video broadcasting (DVB) project, DVB-T2, has recently been standardized. In this article we perform a complexity analysis of our software defined implementation of the modulator/demodulator parts of a DVB-T2 transmitter and receiver. First we describe the various stages of a DVB-T2 modulator and demodulator, as well as how they have been implemented in our system. We then perform an analysis of the computational complexity of each signal processing block. The complexity analysis is performed in order to identify the blocks that are not feasible to run in realtime on a general purpose processor. Furthermore, we discuss implementing these computationally heavy blocks on other architectures, such as GPUs (graphics processing units) and FPGAs (field-programmable gate arrays), that would still allow them to be implemented in software and thus be easily reconfigurable.     

Implementation of LTE system on an SDR platform using CUDA and UHD

In this paper, we present an implementation of a long term evolution (LTE) system on a software defined radio (SDR) platform using a conventional personal computer that adopts a graphic processing unit (GPU) and a universal software radio peripheral2 (USRP2) with a URSP hardware driver (UHD) to implement an SDR software modem and a radio frequency transceiver, respectively. The central processing unit executes C++ control code that can access the USRP2 via the UHD. We have adopted the Ettus Research UHD due to its high degree of flexibility in the design of the transceiver chain. By taking advantage of this benefit, a simple cognitive radio engine has been implemented using libraries provided by the UHD. We have implemented the software modem on a GPU that is suitable for parallel computing due to its powerful arithmetic and logic units. A parallel programming method is proposed that exploits the single instruction multiple data architecture of the GPU. We focus on the implementation of the Turbo decoder due to its high computational requirements and difficulty in parallelizing the algorithm. The implemented system is analyzed primarily in terms of computation time using the compute unified device architecture profiler. From our experimental tests using the implemented system, we have measured the total processing time for a single frame of both transmit and receive LTE data. We find that it takes 5.00 and 8.58 ms for transmit and receive, respectively. This confirms that the implemented system is capable of real-time processing of all the baseband signal processing algorithms required for LTE systems.     

A single-chip tuner for DVB-T

A new architecture is presented for a single-chip tuner for digital terrestrial television, based on existing double conversion and direct conversion topologies. The new design forms part of a mixed-signal Digital Video Broadcasting-Terrestrial (DVB-T) receiver system, employing digital signal processing at baseband to ensure minimal performance requirements for the analog circuitry. To evaluate the potential performance of this new tuner/receiver system, high-level system simulations have been performed, followed by the construction of a prototype DVB-T receiver using a custom-designed analog ASIC which integrates all analog tuner blocks (including channel filtering) on one chip. Measured results from this chip, implemented in a 20-GHz bipolar technology, show an overall third-order input referred intercept point of 116 dB/spl mu/V, a noise figure of 14 dB and an automatic gain control range of 71.4 dB, drawing 250 mA at a 5-V supply.     

A direct-conversion receiver for DVB-H

A fully integrated low-power ultrahigh-frequency (UHF) tuner integrated circuit (IC) design for the digital video broadcasting-handheld (DVB-H) market is presented. A direct-conversion receiver is chosen over classical digital video broadcasting-terrestrial (DVB-T) architectures. The tuner IC covers UHF bands IV/V. The solution is based on a radio frequency integrated circuit (RFIC) and external low-noise amplifier (LNA) to meet the noise figure (NF) specification of 5 dB, IIP3 of 4dBm, and Gain of 89 dB. The IC includes an LNA, dual quadrature mixers, multiple bandwidth baseband (BB) filtering, three 4X voltage-controlled oscillators (VCOs), integer phase-locked loop (PLL), and reference oscillator. The design is implemented in a SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) technology and the die area is 11.5 mm/sup 2/.     

DSP based OFDM demodulator and equalizer for professional DVB-Treceivers

This work treats the design of base-band processing subsystems for professional DVB-T receivers using 1600 MIPS, fixed point DSPs. We show the results about the implementation of OFDM demodulation, channel estimation and equalization functional blocks, for the 2k/8k modes. The adoption of general purpose DSPs provides a great flexibility in the development of different configurations of the receiver. Furthermore it enables the feasibility of adaptive equalization schemes, where the quality of the channel estimation varies according to both channel characteristics and speed of the channel variations. The 16/32 bit fixed point architecture leads to a very low implementation loss, and a careful optimization of the pipeline architecture of the processor allows the receiver to obtain short processing delays. The flexibility of the software approach along with the obtained performance make the proposed implementation very interesting in professional and high-end receivers for interactive, multimedia applications of DVB-T     

Efficient GPU and CPU-based LDPC decoders for long codewords

The next generation DVB-T2, DVB-S2, and DVB-C2 standards for digital television broadcasting specify the use of low-density parity-check (LDPC) codes with codeword lengths of up to 64800 bits. The real-time decoding of these codes on general purpose computing hardware is useful for completely software defined receivers, as well as for testing and simulation purposes. Modern graphics processing units (GPUs) are capable of massively parallel computation, and can in some cases, given carefully designed algorithms, outperform general purpose CPUs (central processing units) by an order of magnitude or more. The main problem in decoding LDPC codes on GPU hardware is that LDPC decoding generates irregular memory accesses, which tend to carry heavy performance penalties (in terms of efficiency) on GPUs. Memory accesses can be efficiently parallelized by decoding several codewords in parallel, as well as by using appropriate data structures. In this article we present the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard??at the high data rates required for television broadcasting??possible on a modern GPU. Furthermore, we also describe a similar decoder implemented on a general purpose CPU, and show that high performance LDPC decoders are also possible on modern multi-core CPUs.     

Real-Time Frequency Estimation of Complex GMSK Signal of Green Communications Devices

Parameter estimation of signals of universal software radio peripheral (USRP) devices is crucial to solve the problem of phase offsets of received signals in distributed beamforming. For systems that will utilize the closed loop feedback algorithm where the receiver needs to send the received signal strength (RSS) values periodically to the beamforming node so as to take advantage of energy conservation, the frequency and phase of these signals should be estimated before smoothening by nonlinear filters. This article presents the estimation of the frequency offsets of a Gaussian minimum shift keying (GMSK) signal from N210 USRP devices in real time by using the Radix-2 fast Fourier transform (FFT) algorithm in GNURadio. For these green communications devices, most of the needed hardware parts have been software defined, thereby reducing the supposed energy consumption. The frequency offsets from reference carrier frequencies of 900 MHz and 2.4 GHz are less than 3 kHz each before the estimation, but the average offsets are 45 Hz and 100 Hz after the estimation, respectively. The high offset value experienced with the 2.4 GHz carrier was due to consistent interference from devices on that same frequency.     

基于AD9244和PCI9054的虚拟无线电接收子系统

虚拟无线电是软件无线电技术一种新的发展趋势,基本思路是利用计算机取代传统软件无线电系统中的DSP芯片,一般采用直接中频采样技术,将采样结果通过PCI总线送入主机内存,由用户软件做后续的信号处理.本文讨论了欠采样技术在中频信号接收系统中的应用,由此提出了一种虚拟无线电接收子系统实现的硬件设计方案,然后对系统中重要芯片的性能进行了介绍,并对系统的控制过程进行了详细说明,最后简要介绍了一些注意事项.