Maximising energy efficiency in 3D multicore systems: a formalised approach

Three-dimensional integrated circuits (3D ICs) present an intriguing challenge for both circuit and system engineers due to their diverse cooling efficiency among the stacked dies. Several recent proposals advocate multiple techniques for thermal management of 3D ICs at different levels of the design, while operating within the confines of thermal heterogeneity. In this article, we analyse for the first time, the role of thermal heterogeneity on the energy efficiency of the system by incorporating temperature dependent leakage power. We develop a novel convex optimisation framework to optimise the energy efficiency in 3D ICs incorporating: (a) leakage aware thermal provisioning using temperature dependent full-chip leakage model, (b) heat flow in vertically stacked systems using a grid based compact thermal model and (c) a concrete application for workload provisioning in 3D multicore systems. Detailed simulation-based experiments with our proposed optimisation framework shows 5–17% improvement in the energy efficiency of a typical multicore system organised as 3D stacked dies.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

Collective laser‐assisted bonding process for 3D TSV integration with NCP

Laser‐assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single‐tier LAB process for 3D through‐silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single‐tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu‐Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.     

On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs

3D integration of ICs is an emerging technology where multiple silicon dies are stacked vertically. The manufacturing itself is based on wafer-to-wafer bonding, die-to-wafer bonding or die-to-die bonding. Wafer-to-wafer bonding has the lowest yield as a good die may be stacked against a bad die, resulting in a wasted good die. Thus the latter two options are preferred to keep yield high and manufacturing costs low. However, these methods require dies to be tested separately before they are stacked. A problem with testing dies separately is that the clock network of a prebond die may be incomplete before stacking. In this paper we present a solution to address this problem. The solution is based on on-die Delay Lock Loop (DLL) implementations that are only activated during testing prebond unstacked dies to synchronize disconnected clock regions. A problem with using DLLs in testing is that they cannot be turned on or off within a single cycle. Since scan-based testing requires that test patterns be scanned in at a slow clock frequency before fast capture clocks are applied, On-Product Clock Generation (OPCG) must be used. The proposed solution addresses the above problems and allows a prebond with an incomplete clock network to be tested with low skew.     

Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling

Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.     

先进的叠层式3D封装技术及其应用前景

采用叠层3D封装技术将使芯片所包含晶体管数目成倍的增加,它不但具有体积小、性能高、功耗低等优点,而且拥有无可比拟的封装效率.对其叠层3D封装的发展趋势、技术特点、技术优势、散热问题以及应用前景等几个方面进行了探讨.     

Chips go vertical [3D IC interconnection]

This article describes 3D ICs. By stacking chips and directly connecting them with vertical wires, chip makers help interconnects keep up with increasing transistor speeds. A 3D IC is a stack of multiple dies with many direct connections tunneling through them, dramatically reducing global interconnect lengths and increasing the number of transistors that are within one clock cycle of each other. The key to the advantage comes from allowing wires to be routed directly between and through the chips. With this approach, the maximum global-interconnect length and the average global-interconnect length both decrease by a factor equal to the square root of the number of dies being stacked. This decreases the bottleneck effect they have on the IC's performance by about the same factor.     

Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via

The objective of this study is to evaluate the strength of silicon dies covered with a polymer film - Ajinomoto Build-up Film (ABF) - through the four-point bending (4PB) test and finite element method (FEM) analysis. With the evaluated strength, the possibility of die-cracking in 3D packages, wherein the thinned stacking dies are covered with ABF, under a thermal cycle condition is further investigated. In this study, a sandwich structure composed of an ABF layer as the intermediate layer between two (1 0 0) silicon substrates is applied in the 4PB test. Additionally, two kinds of bonding pressure are applied in the fabrication of 4PB specimens: 1 and 5 MPa. The force-displacement relation of the specimen is first measured by the 4PB test. On the other hand, the corresponding FEM model is simulated to obtain the relation of the first principal stress and the applied displacement. By comparing the experimental data and simulation results, the strength of the silicon substrate covered with ABF can be evaluated. Moreover, the FEM analysis results of a 10-layered die stacking 3D package show that the stress distribution in each stacking die does not exceed the evaluated strength. In summary, this paper demonstrates that the strength of the silicon substrate covered with soft and elastic material, such as ABF, as dielectric and barrier layer in 3D die stacking packages can be enhanced.     

Experimental and numerical study of 3D stacked dies under forced air cooling and water immersion cooling

3D stacked die structure is a promising architecture to realize small feature size and enhance electronic performance. However, thermal performance in 3D stacked die has aroused extensive attention for its high density integration. In this paper, a stacked dummy die structure integrated with polyimide heater inside is presented to investigate the thermal behavior of 3D stacked dies. One-dimensional thermal resistance network is built and calculated to analyze thermal resistance distribution of the stacked dies. Under natural convection, the thermal resistance of convective heat transfer greatly influences total thermal resistance and limits heat dissipation ability of stacked dies. To significantly reduce the thermal resistance of convective heat transfer, forced air cooling and water immersion cooling have been applied in the stacked die structure. Experiment and numerical simulation have been conducted in this work. In the experiment, forced air cooling and water immersion cooling systems are set up to cool down the stacked die structure. The temperature dependence of the stacked die structure is obtained by thermocouples. The measured thermal resistances between junction and ambient environment of the stacked die structure decrease to 7.6 °C/W under forced air cooling and to 0.6 °C/W under water immersion cooling, respectively. Then heat dissipation abilities of forced convection cooling for the stacked die structure are analyzed. Simulation models are built for experimental validation and further thermal analysis. Temperature influences on the internal structure of the stacked dies with different power map are discussed. The simulation results can well capture the experimental results with 5.8% variation under forced air cooling and with 7.4% variation under water immersion cooling when total power of 3 W is applied.     

一种从激光雷达点云中提取建筑物模型的方法

提出了针对机载激光雷达点云的建筑物三维模型提取方法.首先通过滤波从点云中提取数字地形模型(DTM),再从数字表面模型(DSM)中剔除DTM影响,得到正规化数字表面模型(nDSM);然后通过高程滤波和双边滤波从nDSM中得到建筑物区域;在建筑物几何形状约定下,将建筑物分"层"处理,通过边缘探测与规格化算法得到每"层"建筑物的边缘;边缘点坐标构成了建筑物三维模型的基础.该方法借助数学形态学易于计算机处理的优点,能较为快速、准确地提取建筑物三维模型,适合大规模、快速、对精度要求不高的lidar数据提取.最后通过数据验证了该方法的可行性及有效性.     

Revisiting 3DIC benefit with multiple tiers

3DICs with multiple tiers are expected to achieve large benefits (e.g., in terms of power, area) as compared to conventional planar designs. However, few if any previous works study upper bounds on power and area benefits from 3DIC integration with multiple tiers. In this work, we use the concept of implementation with infinite dimension to estimate upper bounds on power and area benefits achievable by 3DICs versus 2DICs. We observe that the maximum power benefit even with infinite dimension can be only 18% versus 2DIC for particular designs. Such benefits reduce further under assumptions of inter-tier variation. We confirm our observation by performing 3D benefit estimation across various technologies. Our study also indicates that it is typically difficult for pure logic-logic 3D integration to achieve a simultaneous (10%, 10%, 10%) improvement in (performance, power, area/cost) compared to the conventional 2D implementation. In addition, we study power of designs across various dimensions (e.g., pseudo-1D, 2D, 3D with two, three and four tiers).¹ We observe that design power sensitivity to implementation with different dimensions correlates well with placement-based Rent parameter of the netlist. Therefore, placement-based Rent parameter can possibly be a simple indicator of 3D power benefit. Our study also shows that netlist synthesis and optimization should be aware of the target implementation dimension (e.g., 2D versus 3D). Finally, we use a simple example to show that there remain potential large 3DIC benefits versus 2DIC for (block-based) SoC designs.     

Monolithic 3D stacked multiply-accumulate units

The monolithic 3D stacking (M3D) reduces the critical path delay, leveraging 1) short latency of a monolithic inter-tier via (MIV) and 2) short 2D interconnect and cell delay through smaller footprint. In this paper, we propose M3D stacked multiply-accumulate (MAC) units; MAC units have a relatively large number of long wires. With the Samsung 28 nm ASIC library, the M3D stacked MAC units reduce the critical path delay by up to 28.9%, compared to the conventional 2D structure. In addition, the M3D stacked MAC units reduce dynamic energy and leakage power by up to 9.6% and 21.7%, respectively. Compared to the TSV stacked MAC units, the M3D stacked MAC units consume less dynamic energy and leakage power by up to 37.1% and 73.6%, respectively. Though the 3D stacking technology inevitably causes higher peak temperature than the 2D structure, our thermal results show that the peak temperature of the M3D stacking is always lower than that of the TSV-based 3D stacking. Furthermore, when the size of the MAC unit is optimized in convolutional neural network (CNN) applications, the peak temperature of the M3D stacking is 88.3 °C at most, which is still under the threshold temperature.     

Topological Insulator Superlattices

HgTe/CdTe and InAs/GaSb/AlSb superlattices both exhibit a topological insulator transition. In each case, there is an inversion of the s- and p-band ordering for layer thicknesses above a critical value. The resulting topological phase is a 2D bulk insulator at zero temperature, with edges that conduct massless carriers whose direction of motion is locked to their direction of spin. These 1D edge states exhibit essentially dissipationless transport over coherence lengths greater than one micron, with a quantized conductance of e²/h per edge. When a current passes, opposite spins are separated to the two sample edges, giving rise to the so-called quantum spin Hall effect. Effects such as these may be exploited in future low temperature spintronic devices. The edge states in HgTe/CdTe differ from those in InAs/GaSb/AlSb in several ways, due to the type II band alignment and weaker electron–hole hybridization of the III-V superlattice. The former exhibit a simple exponential decay over thousands of Angstroms, while the latter are more strongly confined to the edge, with an oscillating wave function whose period increases with the edge state momentum. In any calculation, the edge state dispersion and the nature of the wave-function depend strongly on the boundary conditions used. A k · p model is presented using standard boundary conditions for the wave function and its derivative, which yields spin polarized edge states with a finite amplitude at the sample edge. The interaction between states at opposite sample edges is also considered.     

相邻层冗余共享的三维存储器成品率优化方法

存储裸片堆叠方案和冗余共享策略对提高三维存储器成品率有重要影响.为提高三维存储器的成品率并且减少行列冗余所需的TSVs数量,提出了一种相邻层冗余共享结构.该冗余共享结构使得每层存储裸片的行列冗余不仅能被本层使用,而且能被相邻层使用.并在此结构的基础上,提出了一种新的存储裸片堆叠方案.该方案通过构建存储裸片的选择限制条件,每次选中适合的存储裸片来堆叠三维存储器以充分利用行列冗余.实验结果表明,与国际上同类方法相比,所提方案有效地提高了三维存储器的成品率,并且减少了行列冗余所需的TSVs数量.     

Nonvolatile Floating‐Gate Memories Based on Stacked Black Phosphorus–Boron Nitride–MoS2 Heterostructures

Research on van der Waals heterostructures based on stacked 2D atomic crystals is intense due to their prominent properties and potential applications for flexible transparent electronics and optoelectronics. Here, nonvolatile memory devices based on floating‐gate field‐effect transistors that are stacked with 2D materials are reported, where few‐layer black phosphorus acts as channel layer, hexagonal boron nitride as tunnel barrier layer, and MoS₂ as charge trapping layer. Because of the ambipolar behavior of black phosphorus, electrons and holes can be stored in the MoS₂ charge trapping layer. The heterostructures exhibit remarkable erase/program ratio and endurance performance, and can be developed for high‐performance type‐switching memories and reconfigurable inverter logic circuits, indicating that it is promising for application in memory devices completely based on 2D atomic crystals.     

Out-Of-Plane Metal Coordination for a True Solvent-Free Building with Molecular Bricks: Dodging the Surface Ligand Effect for On-Surface Vacuum Self-Assembly

The desirable self-assembly (SA) of repeated 2D stacked layers requires a “holistic analysis” of three interconnected components: the electrode, the interface, and the molecular component; among them, the contact interface bears the largest burden responsibilities. Epitaxial growth (EG) of coherent 2D+n stacked heterojunction by solvent-free deposition holds great promise, although the feasibility has never been demonstrated given multiple drawbacks (e.g., surface-ligand effect, SLE). Here, it is demonstrated how a coherent 2D+n (n = 3) layered heterorganic film is grown on an archetypal Fe metal electrode. The groundbreaking achievement is the result of the in-vacuum integration of: i) chemical decoupling of the basal organic layer (a Zn^II-tetraphenylporphyrine, ZnTPP) from the metal electrode, ii) 2D-ordering of the ZnTPP commensurate to the substrate, iii) rigid, stoichiometric, and orthogonally arranged, the molecule-to-molecule coupling between ZnTPP and a ditopic linear bridging ligand (i.e., DPNDI) guided by SA coordination chemistry, and iv) sharp (chemical) termination of the layered film.     

Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

Three‐dimensional (3D) memories using through‐silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die‐selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die‐selection method is proposed for multi‐layer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi‐layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multi‐layer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.     

三维集成技术的现状和发展趋势

给出了三维技术的定义,并给众多的三维技术一个明确的分类,包括三维封装(3D-P)、三维晶圆级封装(3DWLP)、三维片上系统(3D-SoC)、三维堆叠芯片(3D-SIC)、三维芯片(3D-IC)。分析了比较有应用前景的两种技术,即三维片上系统和三维堆叠芯片和它们的TSV技术蓝图。给出了三维集成电路存在的一些问题,包括技术问题、测试问题、散热问题、互连线问题和CAD工具问题,并指出了未来的研究方向。     

3D-TSV技术——延续摩尔定律的有效通途

对于堆叠器件的3-D封装领域而言,硅通孔技术(TSV)是一种新兴的技术解决方案.将器件3D层叠和互连可以进一步加快产品的时钟频率、降低能耗和提高集成度.为了在容许的成本范围内跟上摩尔定律的步伐,在主流器件设计和生产过程中采用三维互联技术将会成为必然.介绍了TSV技术的潜在优势,和制约该技术发展的一些不利因素及业界新的举...     

Thermal‐Aware Floorplanning with Min‐cut Die Partition for 3D ICs

Three‐dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through‐silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal‐aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal‐aware floorplanning with min‐cut die partitioning for 3D ICs. The proposed min‐cut die partition methodology minimizes the number of connections between partitions based on the min‐cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal‐aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run‐time.