Block-based multiperiod dynamic memory design for low data-retention power

Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN/sup 2/) steps our algorithm computes K refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.     

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm². We designed a 1Mb DRAM with an open bit‐line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when V_cc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4×32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode     

选择性BF_2~+离子注入对提高DRAM刷新时间的研究

动态随机存储器(dynamic random access memory,DRAM)电容器在存储高电位数据"1"时,将影响邻近记忆单元区晶体管栅极电场分布,从而导致漏电流增加,降低了刷新时间.研究提出针对位元线接触区、有选择性的浅掺杂漏极离子注入BF2+方案来改善刷新时间,模拟分析了其注入离子分布及电迁移,发现在位元线接触区硅基单侧浅表层形成了富硼离子注入区,且最大电迁移深度仅为60 nm,由此减少了对其它掺杂区的影响.电性测试结果表明,BF2+离子剂量与开启电压成正比,重复实验证明,该方案有良好的可再现性;分析结果表明,增加BF2+离子注入剂量能提高开启电压对制造偏差的容差能力;栅极关键尺寸在(90±15)nm波动范围内晶圆样品的NMOS电性测试结果表明,该离子注入法能保持与原有工艺的良好匹配性.进一步的分析结果指出,若开启电压升高,则刷新时间将会减少,若开启电压为0.8 V时,该离子注入方案能使刷新时间从180ms提升到不小于300ms.改良幅度达66.7%.模拟及实验分析结果表明,该离子注入方案能应用于深微米进程的研究与生产中.     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition. The battery life is the critical problem for wearable devices. The non-volatile memory (NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption, NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory (DRAM). In this paper, we assume to use hybrid random access memory (RAM) and NVM architecture for the smart bracelet system. This paper presents a data management algorithm named bracelet power-aware data management (BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.     

On the retention time distribution of dynamic random access memory(DRAM)

The retention time distribution of high-density dynamic random access memory (DRAM) has been investigated. The key issue for controlling the retention time distribution has been clarified and its model has been proposed for the first time. Trench capacitor cell with 0.6-μm ground rule was evaluated. It was found that the retention time distribution consists of “tail distribution” and “main distribution.” “tail distribution,” by which DRAM refresh characteristics are restricted, depends on the boron concentration of the memory cell region. As boron concentration of the memory cell region increases, “tail distribution” is enhanced. This enhancement is due to the increase of the junction leakage current from the storage node. For the purpose of accounting for the nature of “Tail Distribution,” the concept of thermionic field emission (TFE) current has been introduced. The high electric field at pn junction of the storage node enhances thermionic field emission from a deep level. The activation energy of the deep level is normally distributed among the memory cells, which leads to the normal distribution of log(retention time). Two methods for reducing “tail distribution” are proposed. One is to reduce the electric field of the depletion layer of the storage node. The other is to reduce the concentration of the deep level for TFE current     

The design and performance of CMOS 256K bit DRAM devices

The design and performance of CMOS 256K bit dynamic random access memory devices with 256K/spl times/1 and 64K/spl times/4 output configurations are presented. An advanced CMOS technology, with device scaling to the HMOS-III level, is used to provide effective solutions to critical device and circuit problems in DRAM design and to offer features not previously implemented in NMOS designs. The cell and die area are 70 /spl mu/m/SUP 2/ and 253 mil /spl square/ (6.3 mm /spl square/), respectively. The typical row access time is less than 100 ns. The p-channel memory array used in this design improves the memory refresh characteristics and reduces the soft error rates. The use of static and clocked CMOS circuits provides lower active power, wide operating margins, microwatt standby power, and high column data bandwidth. The 256K bit devices are designed with two output modes, namely, ripplemode and static column mode, selected by a metal mask option.     

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM

Concordant memory design incorporates fluctuation in device parameters statistically into signal-to-noise ratio analysis in DRAM. In this design, the effective signal voltage of all cells in a chip is calculated, and the failed bit count of the chip is estimated. The proposed design approach gives us a quantitative evaluation of the memory array and assures 1.4-V array operation of 100-nm-1-Gb DRAM. Calculated dependence of the failed bit count on the array voltage is in close agreement with measured data for the 512-Mb DRAM chip.     

A 1.6-GByte/s DRAM with flexible mapping redundancy technique andadditional refresh scheme

We implemented 72-Mb direct Rambus DRAM with new memory architecture suitable for multibank. There are two novel schemes: flexible mapping redundancy (FMR) technique and additional refresh scheme. This paper shows that multibank reduces redundancy area efficiency. But with the FMR technique, this 16-bank DRAM realizes the same area efficiency as a single-bank DRAM. In other words, FMR reduces chip area by 13%. This paper also describes that additional refresh scheme reduces data retention power to 1/4. Its area efficiency is about four times better than that of the conventional redundancy approach     

A divided/shared bit-line sensing scheme for ULSI DRAM cores

A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly     

A charge recycle refresh for Gb-scale DRAM's in file applications

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 μm technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells     

Bipolar switching characteristics of low-power Geo resistive memory

We reported an ultra low-power resistive random access memory (RRAM) combining a low-cost Ni electrode and covalent-bond GeO_x dielectric. This cost-effective Ni/GeO_x/TaN RRAM device has very small set power of 2 μW, ultra-low reset power of 130 pW, greater than 1 order of magnitude resistance window, and stable retention at 85 °C. The current flow at low-resistance state is governed by Poole-Frenkel conduction with electrons hopping via defect traps, which is quite different from the filament conduction in metal-oxide RRAM.     

GaAs dynamic memory design

Subthreshold leakage loss is a serious problem for GaAs dynamic memory. Since the leakage current in a MESFET is several orders of magnitude higher than that in a MOSFET, it is difficult to retain the charge at dynamic nodes resulting in data storage errors, In order to solve this problem, a novel DRAM architecture is proposed. The design is based on a cell consisting of a MESFET switch and a metal-insulator-metal (MIM) planar capacitor as the storage element. The leakage current is reduced by a level-shift technique and a self-biased transistor is used to maintain the dynamic charge during the sense period. A high performance sense amplifier is used to detect small bit line voltage changes and refresh the stored data. A 1 Kb prototype, fabricated in a 1 μm nonself-aligned GaAs MESFET technology, exhibited a total read/write access time of the order of 3 ns     

A novel nonvolatile memory based on self-organized quantum dots

A novel type of memory based on self-organized quantum dots (QDs) is presented, which merges the advantages of the most important semiconductor memories, the dynamic random access memory (DRAM) and the Flash. A nonvolatile memory with fast access times and good endurance (>10¹⁵ write/erase cycles) as an ultimate solution seems possible. A storage time of 1.6 s at 300 K in InAs/GaAs QDs with an additional Al_0.9Ga_0.1As barrier is demonstrated and a retention time of 10⁶ years is predicted for GaSb QDs in an AlAs matrix. A minimum write time of 6 ns is obtained for InAs/GaAs QDs. This value is already in the order of the access time of a DRAM cell and at the moment limited by the RC low pass of the device. An erase time of milliseconds is shown in first measurements on GaSb/GaAs QDs at . Faster write/erase times below even at room temperature are expected for improved device structures.     

An 800-MHz embedded DRAM with a concurrent refresh mode

An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.     

Josephson memory technology

Memory circuit architecture (decoder, cell, cell array, and sense circuit) is surveyed, with emphasis on implementing a memory with fast access and low power consumption. Recent progress in fabrication and circuit technology has improved memory performance. An AC powering scheme, instead of the earlier DC system, has been developed. The AC powering scheme eliminates complicated timing control, which restricts shortening access time, but introduces large power consumption and in-phase powering problems. A parallel decoding scheme that decreases the number of decoding stages is presented. It will decrease the decoding time and AND scheme decoder. An attractive OR-inverter scheme has been proposed for a decoder suitable for a memory with a large capacity. The chip performance strongly depends not only on whether the read mode is destructive or nondestructive but also on the cell connection method, which determines the line inductance. Because the cell input line inductance depends on layered construction of the lines, a planarizing technology for an Nb Josephson integrated circuit has been developed to reduce line inductance by thinning the insulators. Access time of less than 0.5 ns has been confirmed in 1-kb and 4-kb memories using the proposed memory architecture     

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25-μm CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 μm². Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm²     

A mechanism for asymmetric data writing failure

As dynamic random access memory (DRAM) technology develops further, it is more difficult to sustain a sufficient sensing margin to detect weak cell data. Therefore, a high data writing performance is necessary in order to guarantee the data sensing margin. In this paper, an analysis of the phenomenon of an asymmetric data writing failure (ADWF) is presented, taking account of a bit line sense amplifier (BLSA) offset, and the failure mechanism has been studied through the use of measurement analysis.