一种高度并行无乘法器结构的二维IDCT协处理器设计

介绍了一种适用于MPEG-4视频简单层解压缩应用的二维IDCT协处理器。该处理器采用Loeffler架构的IDCT快速算法,并使用加法和移位运算代替IDCT快速算法中的浮点乘法运算单元,用高度并行流水VLSI结构加快数据处理速度,采用一维的IDCT单元的复用的方式来实现二维的IDCT运算。在满足处理速度和精度要求的基础上,利用较少的晶体管数目实现了一种高性能的二维IDCT处理器。该方案已经应用于一款SOC芯片中的硬件MMA(多媒体加速单元)中,IDCT的运算精度也得到了验证。     

VLSI design investigation for low-cost, low-power FFT/IFFT processing in advanced VDSL transceivers

The problem of an efficient very large scale integration (VLSI) realization of the direct/inverse fast Fourier transform (FFT/IFFT) for digital subscriber line (DSL) applications is addressed in this paper. The design of scalable and very high-rate (VDSL) modem claims for large and high-throughput complex FFT computations while for massive and fast deployment of the xDSL family low-cost and low-power constraints are key issues. Throughout the paper we explore the design space at different levels (algorithm, arithmetic accuracy, architecture, technology) to achieve the best trade-off between processing performance, hardware complexity and power consumption. A programmable VLSI processor based on a FFT/IFFT cascade architecture plus pre/post-processing stages is discussed and characterized from the high-level choices down to the gate-level synthesis. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the power consumption exploiting the correlation of the FFT/IFFT coefficients and the statistics of the input signals. To this aim both frequency-division and time-division duplex schemes have been considered. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Synthesis results for a 0.18 μm CMOS standard-cells technology show that the processor is suitable for real-time modulation and demodulation in scalable full-rate VDSL modem (64-4096 complex FFT, 20 Msample/s) with a power consumption of few tens of mW. These performances are very interesting when compared to state-of-the-art software implementations and custom VLSI ones.     

Bluetooth-a new low-power radio interface providing short-rangeconnectivity

In the past decades, progress in microelectronics and VLSI technology has fostered the widespread use of computing and communication applications in portable electronic devices. In this paper, we review the Bluetooth technology, a new universal radio interface enabling electronic devices to connect and communicate wirelessly via short-range connections. Motivations for the air interface design and radio requirement decisions are discussed. Frequency hopping, interference resistance, and the concepts of ad hoc connectivity and scatternets are explained in detail. Furthermore, Bluetooth characteristics enabling low-cost single-chip implementations and supporting low power consumption are discussed     

Retinal fundus vasculature multilevel segmentation using whale optimization algorithm

The aim was to present a novel automated approach for extracting the vasculature of retinal fundus images. The proposed vasculature extraction method on retinal fundus images consists of two phases: preprocessing phase and segmentation phase. In the first phase, brightness enhancement is applied for the retinal fundus images. For the vessel segmentation phase, a hybrid model of multilevel thresholding along with whale optimization algorithm (WOA) is performed. WOA is used to improve the segmentation accuracy through finding the \(n{-}1\) optimal n-level threshold on the fundus image. To evaluate the accuracy, sensitivity, specificity, accuracy, receiver operating characteristic (ROC) curve analysis measurements are used. The proposed approach achieved an overall accuracy of 97.8%, sensitivity of 88.9%, and specificity of 98.7% for the identification of retinal blood vessels by using a dataset that was collected from Bostan diagnostic center in Fayoum city. The area under the ROC curve reached a value of 0.967. Automated identification of retinal blood vessels based on whale algorithm seems highly successful through a comprehensive optimization process of operational parameters.     

A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants

This paper describes an area and power-efficient VLSI approach for implementing the discrete wavelet transform on streaming multielectrode neurophysiological data in real time. The VLSI implementation is based on the lifting scheme for wavelet computation using the symmlet4 basis with quantized coefficients and integer fixed-point data precision to minimize hardware demands. The proposed design is driven by the need to compress neural signals recorded with high-density microelectrode arrays implanted in the cortex prior to data telemetry. Our results indicate that signal integrity is not compromised by quantization down to 5-bit filter coefficient and 10-bit data precision at intermediate stages. Furthermore, results from analog simulation and modeling show that a hardware-minimized computational core executing filter steps sequentially is advantageous over the pipeline approach commonly used in DWT implementations. The design is compared to that of a B-spline approach that minimizes the number of multipliers at the expense of increasing the number of adders. The performance demonstrates that in vivo real-time DWT computation is feasible prior to data telemetry, permitting large savings in bandwidth requirements and communication costs given the severe limitations on size, energy consumption and power dissipation of an implantable device.     

Retinal image analysis using curvelet transform and multistructure elements morphology by reconstruction

Retinal images can be used in several applications, such as ocular fundus operations as well as human recognition. Also, they play important roles in detection of some diseases in early stages, such as diabetes, which can be performed by comparison of the states of retinal blood vessels. Intrinsic characteristics of retinal images make the blood vessel detection process difficult. Here, we proposed a new algorithm to detect the retinal blood vessels effectively. Due to the high ability of the curvelet transform in representing the edges, modification of curvelet transform coefficients to enhance the retinal image edges better prepares the image for the segmentation part. The directionality feature of the multistructure elements method makes it an effective tool in edge detection. Hence, morphology operators using multistructure elements are applied to the enhanced image in order to find the retinal image ridges. Afterward, morphological operators by reconstruction eliminate the ridges not belonging to the vessel tree while trying to preserve the thin vessels unchanged. In order to increase the efficiency of the morphological operators by reconstruction, they were applied using multistructure elements. A simple thresholding method along with connected components analysis (CCA) indicates the remained ridges belonging to vessels. In order to utilize CCA more efficiently, we locally applied the CCA and length filtering instead of considering the whole image. Experimental results on a known database, DRIVE, and achieving to more than 94% accuracy in about 50 s for blood vessel detection, proved that the blood vessels can be effectively detected by applying our method on the retinal images.     

基于RAU-net的视网膜血管图像分割

在眼科疾病的诊断中,对视网膜血管进行分割是非常有效的一种方法。在方法使用中,经常会遇到由于视网膜血管背景对比度低及血管末梢细节复杂导致的血管分割难度较大的问题,通过在设计网络的过程中在基础U-net网络中引入残差学习,注意力机制等模块,并将两者巧妙地结合在一起,提出一种新型的基于U-net的RAU-net视网膜血管图像分割算法。首先,在网络的编码器阶段加入残差模块,解决了模型网络加深导致梯度爆炸以及梯度消失的问题。其次,在网络的解码器阶段引入注意力门（attention gate, AU）模块,用来抑制不必要的特征,从而使模型产生更高的精度。通过在DRIVE数据集上进行验证,该算法的准确率、灵敏度、特异性和F₁-score分别达到了0.7832,0.9815,0.9568和0.8192。分割效果相对于普通监督学习算法较为良好。     

Cellular Neural Networks With Virtual Template Expansion for Retinal Vessel Segmentation

A retinal vessel segmentation method based on cellular neural networks (CNNs) is proposed. The CNN design is characterized by a virtual template expansion obtained through a multistep operation. It is based on linear space-invariant 3times3 templates and can be realized using existing chip prototypes like the ACE16K. The proposed design is capable of performing vessel segmentation within a short computation time. It was tested on a publicly available database of color images of the retina, using receiver operating characteristic curves. The simulation results show good performance comparable with that of the best existing methods     

基于多模型融合和区域迭代生长的视网膜血管自动分割

糖尿病视网膜病变是成年人致盲首因,视网膜血管分割是诊断糖尿病视网膜病变的基础.为提高视网膜血管分割准确性,提出一种基于多模型融合和区域迭代生长的视网膜血管自动分割算法.首先,预处理后分别构建数学形态学、匹配滤波器、尺度空间分析、多尺度线检测和神经网络模型初步分割视网膜血管,为减少噪声取五个分割结果的均值作为初步输出.其次,设计掩膜分离渗出物和视盘,将数学形态学模型分割结果替换掩膜白色区域,并融合初步输出生成组合结果.最后,考虑视网膜血管先验知识,对组合结果阈值分割和区域迭代生长后获取最终结果.实验结果表明,该算法分割DRIVE和STARE眼底图像库视网膜血管的检测精度、敏感度和特异性分别为0.9457、0.7843、0.9815以及0.9472、0.7826、0.9803,优于多数经典算法.     

Analog VLSI Circuits for Competitive Learning Networks

An investigation is made concerning implementations of competitive learning algorithms in analog VLSI circuits and systems. Analog and low power digital circuits for competitive learning are currently important for their applications in computationally-efficient speech and image compression by vector quantization, as required for example in portable multi-media terminals. A summary of competitive learning models is presented to indicate the type of VLSI computations required, and the effects of weight quantization are discussed. Analog circuit representations of computational primitives for learning and evaluation of distortion metrics are discussed. The present state of VLSI implementations of hard and soft competitive learning algorithms are described, as well as those for topological feature maps. Tolerance of learning algorithms to observed analog circuit properties is reported. New results are also presented from simulations of frequency-sensitive and soft competitive learning concerning sensitivity of these algorithms to precision in VLSI learning computations. Applications of these learning algorithms to unsupervised feature extraction and to vector quantization of speech and images are also described.     

基于自适应像素分割算法的FPGA设计与实现

为了解决运动目标前景检测的精度问题,提出了一种基于FPGA实现的自适应像素分割系统。该系统通过构建新的背景模型和前景分割检测技术优化检测结果,并对传统的自适应像素分割算法进行了调整和修改,以便在FPGA平台上进行硬件实现。在Xilinx virtex7 FPGA芯片上已完成了硬件测试。试验测试结果显示相比其他算法,本文提出设计的各项性能指标均表现良好,检测精度达到71.4%,平均功耗为6.452 W。能够实现以50 frame/s,实时处理分辨率为720×576的视频流。     

基于强化特征提取的视网膜血管分割

视网膜血管的分割精确率对眼科疾病和糖尿病早期诊断有着重要影响。面对现有方法在微血管与病变区域分割性能差的问题,本文提出一种强化提取血管特征的分割模型。该模型在编码部位引入多尺度特征提取残差模块(multi-scale feature extraction residual module,MFE-residual) 和多级残差空洞卷积层,用来扩展感受野,学习多层次图像特征,提高模型对血管信息的利用率;下采样和短连接部位分别融入轻量化注意力机制和多通道注意力模块,增加模型对血管的识别度,降低误分割的可能性。本文基于DRIVE和STARE两种公开数据集进行了实验,来验证改 进模型的分割能力。结果表明,两种数据上的准确率分别为0.965 2和0.971 5,灵敏度分别为0.820 5和0.825 6,与其他算法相比,分割性能更有优势。     

Analog VLSI implementation of spatio-temporal frequency tuned visual motion algorithms

The computation of local visual motion can be accomplished very efficiently in the focal plane with custom very large-scale integration (VLSI) hardware. Algorithms based on measurement of the spatial and temporal frequency content of the visual motion signal, since they incorporate no thresholding operation, allow highly sensitive responses to low contrast and low-speed visual motion stimuli. We describe analog VLSI implementations of the three most prominent spatio-temporal frequency-based visual motion algorithms, present characterizations of their performance, and compare the advantages of each on an equal basis. This comparison highlights important issues in the design of analog VLSI sensors, including the effects of circuit design on power consumption, the tradeoffs of subthreshold versus above-threshold MOSFET biasing, and methods of layout for focal plane vision processing arrays. The presented sensors are capable of distinguishing the direction of motion of visual stimuli to less than 5% contrast, while consuming as little as 1 /spl mu/W of electrical power. These visual motion sensors are useful in embedded applications where minimum power consumption, size, and weight are crucial.     

一种应用于纳米工艺存储编译器的高效且精确例化功耗表征方法

随着芯片规模的不断增大,功耗成为影响纳米工艺芯片设计性能的主要因素。而在一个典型的千万门级规模SoC设计中,存储器的面积往往占到整个芯片面积的一半以上!因此,除了在实际的芯片设计中实现低功耗设计方法,一种高效准确的对静态和动态功耗的表征方法对于进行设计的功耗预估是非常重要的,尤其是对于便携式应用的芯片项目。在这篇论文中,我们在回顾传统功耗表征方法和其应用限制的同时,将阐述一种不仅可以解决当前功耗表征瓶颈而且具有高准确度的方法。为了达到高精度的设计要求,我们将纳入在纳米工艺下布图相关效应对器件和连线的寄生参数的影响。在文章中我们解释了这种方法的实现流程,并将一些实验结果分享提供读者参考。     

多尺度特征融合双U型视网膜分割算法

视网膜血管形态结构是反映人体健康的重要指标 ,针对现有视网膜血管分割存在主 血管模糊、微细血管断裂和视盘误分割等问题,提出多尺度特征融合双U型视网膜分割算 法。首先,利用低层U-Net高效循环残差模块对眼底图像进行粗粒度分割,得到视网膜血 管 初步轮廓。其次,将粗分割图与原始特征图像素相乘送入高层U-Net,利用其缩放宽残差 模 块进行细粒度图像解码,丰富视网膜血管细节信息。同时利用3路径注意力机制复合性连接 双网络的编码层与解码层,实现特征映射跨网络传播,减小上下文语义差异。最后,融合双 层网络输出提取血管区域,双U 型网络能够更深层次提取血管像素,精准分割出视网膜细 节。在DRIVE与STARE数据集上进行实验,其准确率分别为96.45%和97.02%,敏感度分 别为83.35%和81.40%,特异性分别为98.38%和 98.83%,总体性能优于现有算法。     

基于过渡区提取的视网膜血管分割方法

 针对现有视网膜血管分割方法对于小血管和低对比度血管分割效果差的问题,提出了一种基于过渡区提取的视网膜血管分割方法.该方法首先采用二维高斯匹配滤波预处理以增强血管,然后采用基于最佳熵的方法提取主血管、采用基于分布式遗传算法和Otsu相结合的方法提取过渡区,最后利用区域连通性分析所提取的主血管和过渡区,分割出最终的血管.通过在Hoover眼底图像库中的实验,结果表明该方法在小血管的提取、连通性和有效性方面均优于Hoover算法,另外由于迁移策略的分布式遗传算法的引入,使得算法效率也明显提高.     

Low-Power Finite Impulse Response (FIR) Filter Design Using Two-Dimensional Logarithmic Number System (2DLNS) Representations

In most real-time DSP applications, high performance is a prime target. Here, performance may be interpreted as a combination of higher speed, lower power consumption, sufficient precision, and VLSI area efficiency. It has been experienced that efficient digital multiplication is a prerequisite for high-speed DSP applications. The MDLNS, which has similar properties to the classical LNS, is an alternative approach to conventional number systems for performing multiplication, through using parallel small adders. In addition, by applying recursive multiplication scheme, larger word length multiplication can be performed by use of several small multipliers. The concept of recursive multiplication can be applied to 2DLNS structures, resulting in more efficient digital multipliers. In this work, the recursive 2DLNS-based multipliers have been applied to FIR filter design. These applications demonstrate the superiority of our architectures in terms of VLSI area and power consumption.     

High Speed Energy Efficient Static Segment Adder for Approximate Computing Applications

Real time high quantity digital data computing design needs to achieve high performance with required accuracy range. The constraints involved with high performance are low power consumption, area efficiency and high speed. This paper proposes a design of high speed energy efficient Static Segment Adder (SSA), which improves the overall performance based on static segmentation. Accuracy Adjustment Logic (AAL) is incorporated to improve the accuracy derived from negating lower order bytes of input operands. In this paper, an integration of static segment method and accuracy adjustment logic is used to achieve computational accuracy for error tolerant applications. The proposed adder design enables to provide high speed and energy efficiency through the static segmentation method. Image enhancement operation is carried out using proposed SSA design. In this method, 99.4% overall computational accuracy for 16-bit addition even with 8-bit adder can be achieved.     

VLSI architecture for a low-power video codec system

In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware–software (HW–SW) partitioning assuming power consumption, flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW–SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform.