Parallel canonical recoding

The author introduces a parallel algorithm for generating the canonical signed-digit expansion of an n-bit number in O(log n) time using O(n) gates. The algorithm is similar to the computation of the carries in a carry look-ahead circuit. It is also proven that if the binary number x+[x/2] is given, then the canonical signed-digit recoding of x can be computed in O(1) time using O(n) gates     

Improved lightpath (wavelength) routing in large WDM networks

We address the problem of efficient circuit switching in wide area networks. The solution provided is based on finding optimal routes for lightpaths and semilightpaths. A lightpath is a fully optical transmission path, while a semilightpath is a transmission path constructed by chaining several lightpaths together, using wavelength conversion at their junctions. The problem thus is to find an optimal lightpath/semilightpath in the network in terms of the cost of wavelength conversion and the cost of using the wavelengths on links. In this paper, we first present an efficient algorithm for the problem which runs in time O(k²n+km+kn log(kn)), where n and m are the number of nodes and links in the network, and k is the number of wavelengths. We then analyze that the proposed algorithm requires O(d ²nk₀²+mk₀ log n) time for a restricted version of the problem in which the number of available wavelengths for each link is bounded by k₀ and k₀=o(n), where d is the maximum in-degree or out-degree of the network. It is surprising to have found that the time complexity for this case is independent of k. It must be mentioned that our algorithm can be implemented efficiently in the distributed computing environment. The distributed version requires O(kn) time and O(km) messages. Compared with a previous O(k²n+kn²) time algorithm, our algorithm has the following advantages. (1) We take into account the physical topology of the network which makes our algorithm outperform the previous algorithm. In particular, when k is small [e.g., k=O(log n)] and m=O(n), our algorithm runs in time O(n log² n), while the previous algorithm runs in time O(n log n). (2) Since our algorithm has high locality, it can be implemented on the network distributively     

Polynomial Time Approximation Algorithms for Multi-Constrained QoS Routing

We study the multi-constrained quality-of-service (QoS) routing problem where one seeks to find a path from a source to a destination in the presence of K ges 2 additive end-to-end QoS constraints. This problem is NP-hard and is commonly modeled using a graph with n vertices and m edges with K additive QoS parameters associated with each edge. For the case of K = 2, the problem has been well studied, with several provably good polynomial time-approximation algorithms reported in the literature, which enforce one constraint while approximating the other. We first focus on an optimization version of the problem where we enforce the first constraint and approximate the other K - 1 constraints. We present an O(mn log log log n + mn/epsi) time (1 + epsi)(K - 1)-approximation algorithm and an O(mn log log log n + m(n/epsi)^K-1) time (1 + epsi)-approximation algorithm, for any epsi > 0. When K is reduced to 2, both algorithms produce an (1 + epsi)-approximation with a time complexity better than that of the best-known algorithm designed for this special case. We then study the decision version of the problem and present an O(m(n/epsi)^K-1) time algorithm which either finds a feasible solution or confirms that there does not exist a source-destination path whose first weight is bounded by the first constraint and whose every other weight is bounded by (1 - epsi) times the corresponding constraint. If there exists an H-hop source-destination path whose first weight is bounded by the first constraint and whose every other weight is bounded by (1 - epsi) times the corresponding constraint, our algorithm finds a feasible path in O(m(H/epsi)^K-1) time. This algorithm improves previous best-known algorithms with O((m + n log n)n/epsi) time for K = 2 and 0(mn(n/epsi)^K-1) time for if ges 2.     

子集和问题的量子中间相遇搜索算法

子集和问题是NP完全问题,该问题是背包公钥的基础.现有最优的经典算法求解规模为n的子集和问题需要O(n2n/2)步运算.本文提出了基于时空折衷思想的量子中间相遇搜索算法,该算法可以在O(n2n/3)步求解规模为n的子集和问题,其存储复杂性为O(2n/3).由于NP完全问题可以在多项式时间内可相互归约,所以,在存储复杂性...     

基于自组织特征映射特性的栅阵列排序算法

本文应用自组织特征映射神经网络的竞争学习和自组织特性,并根据栅阵列排序问题的性质来设定网络的竞争原则,建立了一个栅阵列排序算法.实验证明该算法可以求得十分接近全局最优解下限的布图结果.该算法的时间复杂度为O(np2In p),n为线网数,p为主栅列数.     

A high-speed multiplier using a redundant binary adder tree

A 16-bit /spl times/ 16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2.7-/spl mu/m design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log/SUB 2/ n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by N. Takagi et al. (1982, 1983). The 16-bit/spl times/16-bit multiplier chip size is 5.8 /spl times/ 6.3 mm/SUP 2/ using the new layout for a binary adder tree. The chip contains about 10600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. It is estimated that a 32-bit /spl times/ 32-bit multiplication time is about 140 ns.     

An O(k3·log(n/k)) algorithm for theconsecutive-k-out-of-n:F system

The fastest generally-recognized algorithms for computing the reliability of consecutive-k-out-of-n:F systems require O(n) time, for both the linear and circular systems. The authors' new algorithm requires O(k³·log(n/k)) time. The algorithm can be extended to yield an O(n·max{k³·log(n/k), log(n))} total time procedure for solving the combinatorial problem of counting the number of working states, with w working and n-w failed components, w=1,2,...,n     

Maximizing Cooperative Diversity Energy Gain for Wireless Networks

We are concerned with optimally grouping active mobile users in a two-user-based cooperative diversity system to maximize the cooperative diversity energy gain in a radio cell. The optimization problem is formulated as a non-bipartite weighted-matching problem in a static network setting. The weighted-matching problem can be solved using maximum weighted (MW) matching algorithm in polynomial time O(n³). To reduce the implementation and computational complexity, we develop a Worst-Link-First (WLF) matching algorithm, which gives the user with the worse channel condition and the higher energy consumption rate a higher priority to choose its partner. The computational complexity of the proposed WLF algorithm is O(n) while the achieved average energy gain is only slightly lower than that of the optimal maximum weighted- matching algorithm and similar to that of the 1/2-approximation Greedy matching algorithm (with computational complexity of O(n² log n)) for a static-user network. We further investigate the optimal matching problem in mobile networks. By intelligently applying user mobility information in the matching algorithm, high cooperative diversity energy gain with moderate overhead is possible. In mobile networks, the proposed WLF matching algorithm, being less complex than the MW and the Greedy matching algorithms, yields performance characteristics close to those of the MW matching algorithm and better than the Greedy matching algorithm.     

采用基本门单元完全测试矢量的测试生成算法

文章介绍了一种采用基本逻辑门单元的安全测试矢量集生成测试矢量的方法，该方法可以将搜索空间限制在2(n 1）种组合内。它采用故障支配和故障等效的故障传播、回退等技术，建立了一套从局部到全局的测试生成新方法。同时，利用基本门单元安全测试矢量的规律性，可以实现最小的内存容量要求。在一些基准电路的应用实例中，得到了满意的结果。     

Optimization-based placement algorithm for BiCMOS leaf cellgeneration

We present a transistor placement algorithm for the automatic layout synthesis of logic and interface cells comprised of a mixture of MOS and bipolar devices. Our algorithm is applicable to BiCMOS logic cells, ECL logic cells as well as TTL, CMOS and ECL compatible input/output (I/O) cells. The transistor placement problem is transformed into a layout floorplan design problem with a mixture of rigid and flexible modules. A constructive “branch-and-bound” algorithm is used to minimize the area of synthesized circuits subject to pre-placement constraints. Experimental results indicate that the algorithm can produce efficient placements under fixed-height constraints. The design space exploration mechanism can be controlled by the user so as to apportion computing resources judiciously     

Timing driven gate duplication

In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.     

An efficient heuristic for standard-cell placement

A new method is presented for optimization of the one and two-dimensional quadratic assignment problem. The method is suitable for placement problems as they appear in sea-of-gates and standard-cell layout styles for VLSI design. The method is based on recursive partitioning and is a generalization of the method introduced by Kuh et al. It is more flexible than Kuh's method because it does not require a special distribution of the external connections on the boundary of the chip. The time complexity of the algorithm is O(_n Iog²_n). A numerical evaluation of the method is presented, which shows its efficiency for generating near optimal solutions for the quadratic assignment problem as well as for practical standard-cell placement problems.     

基于Tile自组装模型的最大匹配问题算法研究

Tile自组装模型作为一种重要的DNA计算模型,在解决NP问题时展现出了巨大优势.文中针对现有最大匹配问题DNA计算算法实验操作复杂,错误率高的缺点,提出了一种基于Tile自组装模型的最大匹配问题新算法.算法所需的Tile分子种类为O(mn),所需生物操作数为O(1),计算时间为O(m),计算空间复杂度为O(mn)(其中m为边数,n为顶点数,且O(m)=O(n²)).与现有的最大匹配问题DNA计算算法相比,本算法不仅可靠性更好,而且更具可操作性.     

标准单元模式下的一种快速增量式布局算法

增量式布局是适应高性能设计要求的一种新的布局模式 .它针对电路更改 ,局部地调整单元位置 ,重新获得合理的布局 .本文提出了一种标准单元模式下的快速增量布局算法 .算法采用单元行划分的方法处理布局约束 ,然后将布局调整归结为单元依次插入单元行的问题 ,并构造了一个数学规划求解最佳的插入方案 .同时提出了复杂度为O(n)的双对角线搜索法求解这个特殊的数学规划 .实际电路测试表明算法高效而稳定 ,比简单的启发式算法快十倍 ,并使布局修改减少 2 0 %以上     

Space-filling approach for fast window query on compressed images

Based on the space-filling approach, this paper presents a fast algorithm for window query on compressed images. Given a query window of size n/sub 1//spl times/n/sub 2/, the proposed algorithm takes O(n/sub 1/logT+P) time to perform the window query, where n/sub 1/=max(n/sub 1/, n/sub 2/) and T/spl times/T is the image size; P is the number of outputted codes. The proposed algorithm improves the naive algorithm, which needs O(n/sub 1/n/sub 2/log T+P) time, significantly. Some experimentations are carried out to demonstrate the computational advantage of the proposed algorithm. From the experimental results, it is observed that the proposed algorithm has about 72-98% time improvement when compared to the naive algorithm.     

New models and algorithms for future networks

In future networks, transmission and switching capacity will dominate processing capacity. The authors investigate the way in which distributed algorithms should be changed in order to operate efficiently in this new environment. They introduce a class of new models for distributed algorithms which make explicit the difference between switching and processing. Based on these new models they define new message and time complexity measures which, they believe, capture the costs in many high-speed networks more accurately then traditional measures. In order to explore the consequences of the new models, they examine three problems in distributed computation. For the problem of maintaining network topology they devise a broadcast algorithm which takes O(n) messages and O(log n) time for a single broadcast in the new measure. For the problem of leader election they present a simple algorithm that uses O(n) messages and O(n) time. The third problem, distributed computation of a “globally sensitive” function, demonstrates some important features and tradeoffs in the new models and emphasizes and differences with the traditional network model. The results of the present paper influenced later research, as well as the design of IBM Networking Broadband Services (NBBS)     

A dynamic programming algorithm for constructing optimalprefix-free codes with unequal letter costs

We consider the problem of constructing prefix-free codes of minimum cost when the encoding alphabet contains letters of unequal length. The complexity of this problem has been unclear for thirty years with the only algorithm known for its solution involving a transformation to integer linear programming. We introduce a new dynamic programming solution to the problem. It optimally encodes n words in O(n ^C+2) time, if the costs of the letters are integers between 1 and C. While still leaving open the question of whether the general problem is solvable in polynomial time, our algorithm seems to be the first one that runs in polynomial time for fixed letter costs     

Synthesis Scheme for Low Power Designs Under Timing Constraints

To minimize the power consumption with resources operating at multiple voltages a timeconstrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The timeconstrained algorithm has time complexity of Ｏ（ｎ２）,where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46.5%.     

Efficient adaptive algorithms and minimax bounds for zero-delay lossy source coding

Zero-delay lossy source coding schemes are considered for both individual sequences and random sources. Performance is measured by the distortion redundancy, which is defined as the difference between the normalized cumulative mean squared distortion of the scheme and the normalized cumulative distortion of the best scalar quantizer of the same rate that is matched to the entire sequence to be encoded. By improving and generalizing a scheme of Linder and Lugosi, Weissman and Merhav showed the existence of a randomized scheme that, for any bounded individual sequence of length n, achieves a distortion redundancy O(n/sup -1/3/logn). However, both schemes have prohibitive complexity (both space and time), which makes practical implementation infeasible. In this paper, we present an algorithm that computes Weissman and Merhav's scheme efficiently. In particular, we introduce an algorithm with encoding complexity O(n/sup 4/3/) and distortion redundancy O(n/sup -1/3/logn). The complexity can be made linear in the sequence length n at the price of increasing the distortion redundancy to O(n/sup -1/4//spl radic/logn). We also consider the problem of minimax distortion redundancy in zero-delay lossy coding of random sources. By introducing a simplistic scheme and proving a lower bound, we show that for the class of bounded memoryless sources, the minimax expected distortion redundancy is upper and lower bounded by constant multiples of n/sup -1/2/.     

一种基于时间限制条件的低功耗高层综合设计方案

提出了多电压时间限制下电路功耗最小的高层综合设计算法,其输入为数据流图及时间限制条件.由于多电压设计会引起低层布局时的连线复杂性提高,所以提出的算法在进行高层调度过程同时考虑了低层分区问题,即算法利用调度步骤降低功耗,利用分区步骤来减小连线的复杂性.该算法的时间复杂性为O(n2),n是DFG图中的结点个数.大量的DSP基准实验表明该算法使得电路功耗平均降低46.5%.