Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network

The fat-tree is one of the most widely-used topologies by interconnection network manufacturers. Recently, it has been demonstrated that a deterministic routing algorithm that optimally balances the network traffic can not only achieve almost the same performance than an adaptive routing algorithm but also outperforms it. On the other hand, fat-trees require a high number of switches with a non-negligible wiring complexity. In this paper, we propose replacing the fat--tree by a unidirectional multistage interconnection network (UMIN) that uses a traffic balancing deterministic routing algorithm. As a consequence, switch hardware is almost reduced to the half, decreasing, in this way, the power consumption, the arbitration complexity, the switch size itself, and the network cost. Preliminary evaluation results show that the UMIN with the load balancing scheme obtains lower latency than fat--tree for low and medium traffic loads. Furthermore, in networks with a high number of stages or with high radix switches, it obtains the same, or even higher, throughput than fat-tree.     

Learning automata-based bus arbitration for shared-medium ATM switches

Although new high-bandwidth network technologies are being introduced and widely deployed, asynchronous transfer mode (ATM) is still considered one of the most important network technologies currently in use. A number of ATM switch architectures have been proposed in the literature. However, industry has shown that is better to use the well-known shared-medium technique in the design of these ATM switches. In this paper, four variations of a new distributed scheme are proposed for the arbitration of a shared bus of an ATM switch. These schemes are based on learning automata. By taking advantage of the bursty nature of ATM traffic, the new arbitration scheme demonstrates superb performance compared to the time division multiple access (TDMA) scheme.     

Results from the Macramé 1024 node switching network

The work reported involves the construction of a large modular testbed using IEEE 1355 DS link technology. A thousand nodes will be interconnected by a switching fabric based on the STC104 packet switch. The system has been designed and constructed in a modular way in order to allow a variety of different network topologies to be investigated. Network throughput and latency have been studied for different network topologies under various traffic conditions. We also present results of studies carried out with traffic patterns expected for the ATLAS second level trigger system.     

Reliability and Survivability Analysis of Data Center Network Topologies

The architecture of several data centers have been proposed as alternatives to the conventional three-layer one. Most of them employ commodity equipment for cost reduction. Thus, robustness to failures becomes even more important, because commodity equipment is more failure-prone. Each architecture has a different network topology design with a specific level of redundancy. In this work, we aim at analyzing the benefits of different data center topologies taking the reliability and survivability requirements into account. We consider the topologies of three alternative data center architecture: Fat-tree, BCube, and DCell. Also, we compare these topologies with a conventional three-layer data center topology. Our analysis is independent of specific equipment, traffic patterns, or network protocols, for the sake of generality. We derive closed-form formulas for the Mean Time To Failure of each topology. The results allow us to indicate the best topology for each failure scenario. In particular, we conclude that BCube is more robust to link failures than the other topologies, whereas DCell has the most robust topology when considering switch failures. Additionally, we show that all considered alternative topologies outperform a three-layer topology for both types of failures. We also determine to which extent the robustness of BCube and DCell is influenced by the number of network interfaces per server.     

Symmetric crossbar arbiters for VLSI communication switches

The design and implementation of symmetric crossbar arbiters are addressed. Several arbiter designs are compared based on simulations of a multistage interconnection network. These simulations demonstrate the influence of the switch arbitration policy on network throughput, average latency, and worst-case latency. It is shown that some natural designs result in poor system performance and/or slow implementations. Two efficient arbiter implementations are proposed. Based on network simulations, VLSI implementation, and circuit simulation, it is shown that these arbiters achieve nearly optimal system performance without becoming the critical path that limits the system clock     

广域光传送网逻辑拓扑的优化设计

基于波分复用的光组网技术是下一代传送网的最佳解决方案，分组业务光传送网结构设计的核心是虚拓扑的最优化问题．描述了最优虚拓扑问题的主要特点，提出了一种广域光传送网优化虚拓扑的设计原则，优化的目标是使吞吐量最大并且使延迟最小,并采用Prufer数的方法来随机产生一组可行的虚拓扑算法，给出了将虚拓扑嵌入到给定的物理网络的一种启发式算法，并使用遗传算法(GA)来优化虚拓扑，从而得到最优解．光传送网虚拓扑的设计问题在实践上非常重要，提出的方法对于实践者具有重要的指导作用．     

OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees

High-speed interconnection networks are essential elements for different high-performance parallel-computing systems. One of the most common interconnection network topologies is the fat-tree, whose advantages have turned it into the favorite topology of many interconnect designers. One of these advantages is the possibility of using simple but efficient routing algorithms, like the recently proposed deterministic routing algorithm referred to as DET, which offers similar (or better) performance than Adaptive Routing while reducing complexity and guaranteeing in-order packet delivery. However, as other deterministic routing proposals, DET cannot react when packets intensely contend for network resources, leading to the appearance of Head-of-Line (HoL) blocking which spoils network performance. In this paper, we describe and evaluate a simple queue scheme that efficiently reduces HoL-blocking in fat-trees using the DET routing algorithm, without significantly increasing switch complexity and required silicon area. Additionally, we propose an implementation of OBQA in a feasible switch architecture.     

Uniform synchronization in multi‐agent systems with switching topologies

This paper deals with uniform synchronization analysis of multi‐agent systems with switching topologies. The agents are assumed to have general, yet identical, linear dynamics. The underlying communication topology may switch arbitrarily within a finite set of admissible topologies. We establish conditions under which the network is uniformly synchronized meaning that synchronization is valid under all possible switching scenarios. The primary conditions established are in terms of a pair of Lyapunov strict inequalities. Following those conditions, small gain and passivity types of conditions are proposed under which uniform synchronization is guaranteed. The proposed results are also extended to the case of observer‐based protocols. Copyright © 2015 John Wiley & Sons, Ltd.     

Arbiter synthesis approach for SoC multi-processor systems

The increasing complexity of Multi-Processor System on Chip (MPSoC) is requiring communication infrastructures that will efficiently accommodate the communication needs of the integrated computation resources. Exploring the arbitration space is crucial for achieving low latency communication. This paper illustrates an arbiter synthesis approach that allows a high performance MPSoC communication for multi-bus and Network on Chip (NoC) architectures. A cost function has been formulated in order to affect the priority order to each component or each set of components in a manner that minimizes the communication latency and generates a multi-level arbiter. The performance of the proposed approach have been analyzed in a design of an 8 × 8 ATM switch subsystem and a MPEG4 decoder mapped onto a 2-D mesh NoC. The results demonstrate that the MPSoC arbiter is well suited to provide high priority communication traffic with low latencies by allowing a preemption of lower priority transport. The sum of the mean waiting time at the eight ports of the ATM switch is minimum under the MPSoC arbitration scheme (4.30 cycle per word) while it is 3.00 times larger under the poorer performance arbitration scheme. In the case of the MPEG4 decoder, the average packet latency of the MPSoC is about 480 cycles while it is 640 cycles in the poorer performance arbitration scheme under a 0.4 flits/cycle injection rate.     

手动网络拓扑的B/S模式实现

比较了手动网络拓扑和自动网络拓扑的优缺点,指出手动网络拓扑仍是不可缺少的管理方式。讨论了B/S模式实现网络拓扑的两种方案,并选择网络和服务器的负担较小的方案来实现。介绍了SVG,JavaScript,XML-RPC,JSP和Java的B/S方式的实现方案,并解决了以下关键性问题:结点和线路如何与SVG图形元素对应问题;远程数据如何传输;客户端根据远程数据如何将状态实时显示在SVG图形上。给出了采用这一方法的手动网络拓扑的设计和实现,以及应用效果。     

网络并行超级计算系统THNPSC—1

网络并行计算（也称集群式计算）是实现高性能计算的重要方式,该文介绍了一个清华大学研制的网络并行超级计算系统THNPSC－1,它是由Pentium Ⅲ SMP计算结点组成;网络互联采用两种高速网：一种是自制的具有动态仲裁与路由寻经的交叉开关网络THNet,另一种是100Mpbs的Ethernet.THNet中的交叉开关THSwitch是用15万门的ALTERA FPGA芯片构成,THNet还包括具有DMA引擎的网络适配器THNIA.THNet每一端口可以提供数据传输率为1．056Gbps,其聚合频宽可达8．4Gbps;采用固定用户缓冲和扩展的主动消息传递等法,THNet执行用户层的消息传递,旁路操作系统的系统调用,做到零拷贝的消息传递,乒乓测试结果表明：单向消息传递延迟可减少到8μs。THNetl软件包括THNIA驱动程序和支持用户层通信的函数库。此文对相关工作进行了简要对比,并说明了该系统的应用情况。     

Parallel computer vision on a reconfigurable multiprocessor network

A novel reconfigurable architecture based on a multiring multiprocessor network is described. The reconfigurability of the architecture is shown to result in a low network diameter and also a low degree of connectivity for each node in the network. The mathematical properties of the network topology and the hardware for the reconfiguration switch are described. Primitive parallel operations on the network topology are described and analyzed. The architecture is shown to contain 2D mesh topologies of varying sizes and also a single one factor of the Boolean hypercube in any given configuration. A large class of algorithms for the 2D mesh and the Boolean n-cube are shown to map efficiently on the proposed architecture without loss of performance. The architecture is shown to be well suited for a number of problems in low and intermediate level computer vision such as the FFT, edge detection, template matching, and the Hough transform. Timing results for typical low and intermediate level vision algorithms on a transputer based prototype are presented     

Multiprocessor scheme with application to macro-dataflow

A method of operating a multiprocessor system consisting of a large number of processors accessing a common memory is presented. Access to the memory is performed in a deterministic manner which eliminates the need for arbitration logic. An analysis of the method is given and a comparison made against crossbar switch and common bus systems with serial daisy chain and parallel arbitration logic. The key feature of the method is that the memory offers access to locations rather than the processors making asynchronous requests. The scheme has particular application to macro-dataflow when a common memory is used to hold function parameters.     

基于输入缓冲的交换结构研究

研究了交换控制电路中基于输入缓冲的交换结构，提出了一种请求移位的方法处理输入缓冲和中央仲裁器之间的仲裁延时；输入缓冲交换结构的实现采用流水线方式，以减少数据发送请求和应答之间的延时。     

移动Ad hoc网络拓扑结构抗毁性测度模型

引入一种新的抗毁性指标——自然连通度,建立了考虑能耗的移动Ad hoc网络拓扑结构抗毁性综合测度模型,在此基础上确定了基于网络拓扑结构抗毁性的最优发射半径。实验分析表明,该测度模型能有效刻画移动Ad hoc网络拓扑结构的抗毁性,具有最优发射半径的网络拓扑结构能较好权衡网络结构抗毁性和网络生命期。     

基于拥塞预测的NoC自适应仲裁方法*

传统用于总线系统或互联网的仲裁方法已不能很好地适应NoC应用环境。围绕NoC系统性能的关键影响因素——拥塞状态,提出了一种基于全局和本地拥塞预测的仲裁策略(GLCA),以改善NoC网络延迟。实验结果表明,相对于RR方法,新仲裁算法使得网络平均包延迟和平均吞吐量最大分别可改善20.5%和8%,并且在不同负载条件下都保持了其优势。综合结果显示, GLCA与RR方法相比,路由器仅在组合逻辑上有少许增加(25.7%)。     

基于Crossbar交换结构的虚输出队列研究

交换结构及队列调度算法是影响交换机性能的主要因素。此文对基于C rossbar结构的虚输出队列（VOQ）模型从交换结构、 排列模型、实现原理、吞吐率和调度算法方面进行了分析和研究，为构造高带宽的交换机提供了有意义的结论。     

HIPIQS: a high-performance switch architecture using input queuing

Switch-based interconnects are used in a number of application domains, including parallel system interconnects, local area networks, and wide area networks. However, very few switches have been designed that are suitable for more than one of these application domains. Such a switch must offer both extremely low latency and very high throughput for a variety of different message sizes. While some architectures with output queuing have been shown to perform extremely well in terms of throughput, their performance can suffer when used in systems where a significant portion of the packets are extremely small. On the other hand, architectures with input queuing offer limited throughput or require fairly complex and centralized arbitration that increases latency. In this paper, we present a new input queue-based switch architecture called HIPIQS (HIgh-Performance Input-Queued Switch). It offers low latency for a range of message sizes and provides throughput comparable to that of output queuing approaches. Furthermore, it allows simple and distributed arbitration. HIPIQS uses a dynamically allocated multiqueue organization, pipelined access to multibank input buffers, and small cross-point buffers to deliver high performance. Our simulation results show that HIPIQS can deliver performance close to that of output queuing approaches over a range of message sizes, system sizes, and traffic. The switch architecture can therefore be used to build high performance switches that are useful for both parallel system interconnects and for building computer networks     

Energy-aware IP traffic engineering with shortest path routing

Internet energy consumption is rapidly becoming a critical issue due to the exponential traffic growth and the rapid expansion of communication infrastructures worldwide. We address the problem of energy-aware intra-domain traffic engineering in networks operated with a shortest path routing protocol. We consider the problem of switching off (putting in sleep mode) network elements (links and routers) and of adjusting the link weights so as to minimize the energy consumption as well as a network congestion measure. To tackle this multi-objective optimization problem with priority (first minimize the energy consumption and then the network congestion), we propose a Mixed Integer Linear Programming based algorithm for Energy-aware Weights Optimization (MILP-EWO). Our heuristic exploits the Interior Gateway Protocol Weight Optimization (IGP-WO) algorithm for optimizing the OSPF link weights so as to minimize the total cost of link utilization. The computational results obtained for eight real network topologies and different types of traffic matrices show that it is possible to switch off a substantial number of nodes and links during low and moderate traffic periods, while guaranteeing that network congestion is low enough to ensure service quality. The proposed approach is also validated on two networks of emulated Linux routers.     

Controller placement in software defined networks using multi-objective antlion algorithm

Software defined network (SDN) is a new modern network technology which decouples control plane and data plane to simplify network management. The separation of control plane from data plane arises the control placement problem (CPP) in these networks. The main questions in the CPP are (1) how many controllers are required to be used in such networks and (2) where these controllers should be placed. To achieve an efficient solution for such problem in SDN, we define the CPP as a multi-objective combinational optimization problem in this paper and solve the CPP by applying the antlion optimization algorithm on it. We consider three metrics for the CPP: (a) Inter-controllers latency, (b) switch to controller latency, and (c) multiple disjoint connectivity paths between switches and controllers. We evaluate our proposed solution by performing several experiments using different real network topologies. Experimental results show that our proposed solution provides better performance compared to the existing solutions.