基于多Agent的可重构制造系统集成模型

应用控制、管理和维护一体化的自动化技术,建立了基于多Agent的可重构制造系统RMS（Reconfigurable Manufacturing System）集成模型。该模型集成了基于多Agent 的RMS重构模型、控制模型和故障诊断模型,将RMS的控制、管理和维护联系起来,并给出了该模型的UML（Unified Modeling Langurage）活动图,最后举例验证了模型的可行性。     

Continuity aspects of embedded reconfigurable computing

In embedded systems, dynamically reconfigurable computing can be partially modified at runtime without stopping the operation of the whole system. In this paper, we consider a reorganization mechanism for dynamically reconfigurable computing in embedded systems to guarantee that invariants of the design are respected. This reorganization is considered as a visual transformation of the logical configuration by the formulated rules. The invariant is recognized under the restructuring of the configuration using reconfiguration rules.     

Rapid response manufacturing through a rapidly reconfigurable robotic workcell

This article describes the development of a component-based technology robot workcell that can be rapidly configured to perform a specific manufacturing task. The workcell is conceived with standard and inter-operable components including actuator modules, rigid link connectors and tools that can be assembled into robots with arbitrary geometry and degrees of freedom. The reconfigurable “plug-and-play” robot kinematic and dynamic modeling algorithms are developed. These algorithms are the basis for the control and simulation of reconfigurable robots. The concept of robot configuration optimization is introduced for the effective use of the rapidly reconfigurable robots. Control and communications of the workcell components are facilitated by a workcell-wide TCP/IP network and device-level CAN-bus networks. An object-oriented simulation and visualization software for the reconfigurable robot is developed based on Windows NT. Prototypes of the robot workcells configured to perform the light-machining task and the positioning task are constructed and demonstrated.     

Macro-programmable reconfigurable stream processor for collaborative manufacturing systems

Growing demand for high speed processing of streamed data (e.g. video-streams, digital signal streams, communication streams, etc.) in the advanced manufacturing environments requires the adequate cost-efficient stream-processing platforms. Platforms based on the embedded microprocessors often cannot satisfy performance requirements due to limitations associated with the sequential nature of data execution process. During the last decade, development and prototyping of the above embedded platforms has started moving towards utilization of the Field Programmable Gate Array (FPGA) devices. However, the programming of an application to the FPGA based platform became an issue due to relatively complicated hardware design process. The paper presents an approach which allows simplification of the application programming process by utilization of: (i) the uniformed FPGA platform with the dynamically reconfigurable architecture, (ii) a programming technique based on a temporal partitioning of the application in segments which can be described in terms of macro-operators (function specific virtual components). The paper describes the concept of the approach, presents the analytical investigation and experimental verification of the cost-effectiveness of the proposed platform comparing to the platforms based on sequential micro-processors. It is also shown that the approach can be beneficially utilized in collaborative design and manufacturing.     

The case for reconfigurable hardware in wearable computing

Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.     

A programmable spike-timing based circuit block for reconfigurable neuromorphic computing

A generic programmable spike-timing based circuit which forms the building block of a reconfigurable neuromorphic array is implemented in analog VLSI. An array of programmable spike time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 event blocks is fabricated using Austria Microsystems m CMOS technology to demonstrate the functionality of the circuits in silicon.     

Portable library development for reconfigurable computing systems: A case study

Portable libraries of highly-optimized hardware cores can significantly reduce the development time of reconfigurable computing applications. This paper presents the tradeoffs and challenges in the design of such libraries. A set of library development guidelines is provided, which has been validated with the RCLib case study. RCLib is a set of portable libraries with over 100 cores, targeting a wide range of applications. RCLib portability has been verified in three major High-Performance reconfigurable computing architectures: SRC6, Cray XD1 and SGI RC100. Compared to full-software implementations, applications using RCLib hardware acceleration cores show speedups ranging from one to four orders of magnitude.     

A reconfigurable computing framework for multi-scale cellular image processing

Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. These architectures are a good match for many image and video processing applications and can be substantially accelerated with Reconfigurable Computers. We present a flexible software/hardware framework for design, implementation and automatic synthesis of cellular image processing algorithms. The system provides an extremely flexible set of parallel, pipelined and time-multiplexed components which can be tailored through reconfigurable hardware for particular applications. The most novel aspects of our framework include a highly pipelined architecture for multi-scale cellular image processing as well as support for several different pattern recognition applications. In this paper, we will describe the system in detail and present our performance assessments. The system achieved speed-up of at least 100× for computationally expensive sub-problems and 10× for end-to-end applications compared to software implementations.     

A virtual prototyping system with reconfigurable actuators for multi-material layered manufacturing

Proliferation of layered manufacturing (LM) in various sectors has been calling for fabrication of large, complex products with more materials and efficiency. We address this issue by integrating reconfigurable manufacturing (RM) with LM. This paper first analyses the benefits of such integration, and then presents a virtual prototyping system with reconfigurable actuators (VPRA) that can increase the number of materials, speed, and build volume to improve the efficiency and flexibility of multi-material layered manufacturing (MMLM). The VPRA system offers a test bed for design, visualization, and validation of MMLM facilities and processes. It takes advantage of the convenient graphics platform of SolidWorks™ for constructing a virtual MMLM facility by selecting reconfigurable actuators from predefined templates. The characteristics, including the dimensions and relative spatial constraints, of the actuators can be conveniently configured to suit design requirements. The mechanism and the operation process of the resulting MMLM facility can then be simulated and validated through digital fabrication of complex objects. Case studies are presented to demonstrate some possible applications of the VPRA system. Overall, the VPRA system gives insights into the characteristics of a reconfigurable MMLM system, which can be subsequently materialized for physical fabrication of multi-material objects. This approach highlights a possible direction for development of MMLM technology.     

Performance analysis challenges and framework for high-performance reconfigurable computing

Reconfigurable computing (RC) applications employing both microprocessors and FPGAs have potential for large speedup when compared with traditional (software) parallel applications. However, this potential is marred by the additional complexity of these dual-paradigm systems, making it difficult to identify performance bottlenecks and achieve desired performance. Performance analysis concepts and tools are well researched and widely available for traditional parallel applications but are lacking in RC, despite being of great importance due to the applications’ increased complexity. In this paper, we explore challenges and present new techniques in automated instrumentation, runtime measurement, and visualization of RC application behavior. We also present ideas for integration with conventional performance analysis tools to create a unified tool for RC applications as well as our initial framework for FPGA instrumentation and measurement. Results from a case study are provided using a prototype of this new tool.     

A novel methodology to measure the responsiveness of RMTs in reconfigurable manufacturing system

Reconfigurable manufacturing systems are designed to deliver exact functionality and capacity that is needed, when it is needed. The reconfigurable machine tool (RMT) plays a pivotal role in the accomplishment of this objective through their built in modular structure consisting of basic and auxiliary modules along with the open architecture software.     

Towards a generic design method for reconfigurable manufacturing systems: Analysis and synthesis of current design methods and evaluation of supportive tools

In today’s global manufacturing environment, changes are inevitable and something that every manufacturer must respond to and take advantage of, whether it is in regards to technology changes, product changes, or changes in the manufacturing processes. The reconfigurable manufacturing system (RMS) meets this challenge through the ability to rapidly and efficiently change capacity and functionality, which is the reason why it has been widely labelled the manufacturing paradigm of the future. However, design of the RMS represents a significant challenge compared to the design of traditional manufacturing systems, as it should be designed for efficient production of multiple variants, as well as multiple product generations over its lifetime. Thus, critical decisions regarding the degree of scalability and convertibility of the system must be considered in the design phase, which affects the abilities to reconfigure the system in accordance with changes during its operating lifetime. However, in current research it is indicated that conventional manufacturing system design methods do not support the design of an RMS and that a systematic RMS design method is lacking, despite the fact that numerous contributions exist. Moreover, there is currently only limited evidence for the breakthrough of reconfigurability in industry. Therefore, the research presented in this paper aims at synthesizing current contributions into a generic method for RMS design. Initially, currently available design methods for RMS are reviewed, in terms of classifying and comparing their content, structure, and scope, which leads to a synthesis of the reviewed methods into a generic design method. In continuation of this, the paper includes a discussion of practical implications related to carrying out the design, including an identification of potential challenges and an assessment of which tools that can be applied to support the design. Conclusively, further areas for research are indicated, which provides valuable knowledge of how to develop and realize the benefits of reconfigurability in industry.     

可重构制造系统的可重构控制器

可重构控制器是可重构制造系统的重要组成部分之一。该文提出了可重构控制器的体系结构。分析了实现可重构制造系统的可重构控制的方法。仿真研究表明可重构控制是实现可重构制造系统控制系统可重构的有效方法。     

Simulated annealing with auxiliary knowledge for process planning optimization in reconfigurable manufacturing

In this paper, three simulated annealing based algorithms that exploit auxiliary knowledge in different ways are devised and employed to handle a manufacturing process planning problem for reconfigurable manufacturing. These algorithms are configured based on a generic combination of the simulated annealing technique with; (a) heuristic knowledge, and (b) metaknowledge. Capabilities of the implemented algorithms are tested and their performances compared against a basic simulated annealing algorithm. Computational and optimization performances of the implemented algorithms are investigated and analyzed for two problem sizes. Each problem size consists of five different forms of a manufacturing process planning problem. The five forms are differentiated by five alternative objective functions. Experimental results show that the implemented simulated annealing algorithms are able to converge to good solutions in reasonable time. A computational analysis indicates that significant improvements towards a better optimal solution can be gained by implementing simulated annealing based algorithms that are supported by auxiliary knowledge.     

A non-dominated sorting genetic algorithm based approach for optimal machines selection in reconfigurable manufacturing environment

This paper deals with a problem of reconfigurable manufacturing systems (RMSs) design based on products specifications and reconfigurable machines capabilities. A reconfigurable manufacturing environment includes machines, tools, system layout, etc. Moreover, the machine can be reconfigured to meet the changing needs in terms of capacity and functionality, which means that the same machine can be modified in order to perform different tasks depending on the offered axes of motion in each configuration and the availability of tools. This problem is related to the selection of candidate reconfigurable machines among an available set, which will be then used to carry out a certain product based on the product characteristics. The selection of the machines considers two main objectives respectively the minimization of the total cost (production cost, reconfiguration cost, tool changing cost and tool using cost) and the total completion time. An adapted version of the non- dominated sorting genetic algorithm (NSGA-II) is proposed to solve the problem. To demonstrate the effectiveness of the proposed approach on RMS design problem, a numerical example is presented and the obtained results are discussed with suggested future research.     

A transparent and adaptive reconfigurable system

In the current scenario, where computer systems are characterized by a high diversity of applications coexisting in a single device, and with the stagnation in frequency scaling because of the excessive power dissipation, reconfigurable systems have already proven to be very effective. However, they all present two major drawbacks, which are addressed by this work: lack of transparency (the need for special tools or compilers that changes the original code) and no ability to adapt to applications with different behaviors and characteristics, so significant gains are achieved only in very specific data stream oriented applications. Therefore, this work proposes the Dynamic Instruction Merging (DIM), a Binary Translation mechanism responsible for transforming sequences of instructions into a coarse-grained array configuration at run-time, in a totally transparent process, with support to speculative execution. The proposed system does not impose any kind of modification to the source or binary codes, so full binary compatibility is maintained. Moreover, it can optimize any application, even those that do not present specific kernels for optimization. DIM presents, on average, 2.7 times of performance gains and 2.35 times of energy savings over a MIPS processor, and a higher IPC than an out-of-order superscalar processor, running the MIBench benchmark set.     

SOA in reconfigurable supply chains: A research roadmap

Originally coming from the business world, service-oriented architecture (SOA) paradigm is expanding its range of application into several different environments. Industrial automation is increasingly interested on adopting it as a unifying approach with several advantages over traditional automation. In particular, the paradigm is well indicated to support agile and reconfigurable supply chains due to its dynamic nature. In this domain, the main goals are short time-to-market, fast application (re)configurability, more intelligent devices with lifecycle support, technology openness, seamless IT integration, etc. The current research challenges associated to the application of SOA into reconfigurable supply chains are enumerated and detailed with the aim of providing a roadmap into a major adoption of SOA to support agile reconfigurable supply chains.     

A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

We address routing in Networks-On-Chip (NoC) architectures that use irregular mesh topologies with Long-Range Links (LRL). These topologies create difficult conditions for routing algorithms, as standard algorithms assume a static, regular link structure and exploit the uniformity of regular meshes to avoid deadlock and maintain routability. We present a novel routing algorithm that can cope with these irregular topologies and adapt to run-time LRL insertion and topology reconfiguration. Our approach to accommodate dynamic topology reconfiguration is to use a new technique that decomposes routing relations into two stages: the calculation of output ports on the current minimal path and the application of routing restrictions designed to prevent deadlock. In addition, we present a selection function that uses local topology data to adaptively select optimal paths.The routing algorithm is shown to be deadlock-free, after which an analysis of all possible routing decisions in the region of an LRL is carried out. We show that the routing algorithm minimises the cost of sub-optimally placed LRL and display the hop savings available. When applied to LRLs of less than seven hops, the overall traffic hop count and associated routing energy cost is reduced. In a simulated 8 × 8 network the total input buffer usage across the network was reduced by 6.5%.     

Constant-time algorithm for computing the Euclidean distance maps of binary images on 2D meshes with reconfigurable buses

The computation of Euclidean distance maps (EDM), also called Euclidean distance transform, is a basic operation in computer vision, pattern recognition, and robotics. Fast computation of the EDM is needed since most of the applications using the EDM require real-time computation. It is shown in L. Chen and H.Y.H. Chuang [Information Processing Letters, 51, pp. 25–29 (1994)] that a lower bound Ω(n²) is required for any sequential EDM algorithm due to the fact that in any EDM algorithm each of the n² pixels has to be scanned at least once. Recently, many parallel EDM algorithms have been proposed to speedup its computation. Chen and Chuang proposed an algorithm for computing the EDM on an n×n mesh in O(n) time [L. Chen and H.Y.H. Chuang Parallel Computing, 21, pp. 841–852 (1995)]. Clearly, the VLSI complexities of both the sequential and the mesh algorithm described in L. Chen and H.Y.H. Chuang [Parallel Computing, 21, pp. 841–852 (1995)] are AT²=O(n⁴), where A is the VLSI layout area of the design and T is the computation time using area A when implemented in VLSI. In this paper, we propose a new and faster parallel algorithm for computing the EDM problem on the reconfigurable VLSI mesh model. For the same problem, our algorithm runs in O(1) time on a two-dimensional n²×n² reconfigurable mesh. We show that the VLSI complexity of our algorithm is the same as those of the above sequential algorithm and the mesh algorithm, while it uses much less time. To our best knowledge, this is the first constant-time EDM algorithm on any parallel computational model.